Phillip J Nigh

Person

Williston, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Online multiprocessor system reliability defect testing
- Patent number 8,176,362
- Issue date May 8, 2012
- International Business Machines Corporation
- Monty M Denneau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit testing methods using well bias modification
- Patent number 7,759,960
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Grant
Functional pattern logic diagnostic method
- Patent number 7,574,644
- Issue date Aug 11, 2009
- International Business Machines Corporation
- Donato Forlenza
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit testing methods using well bias modification
- Patent number 7,564,256
- Issue date Jul 21, 2009
- International Business Machines Company
- Anne Gattiker
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit testing method using well bias modification
- Patent number 7,486,098
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Anne Gattiker
- G01 - MEASURING TESTING
Information Patent Grant
Testing using independently controllable voltage islands
- Patent number 7,428,675
- Issue date Sep 23, 2008
- International Business Machines Corporation
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit testing methods using well bias modification
- Patent number 7,400,162
- Issue date Jul 15, 2008
- International Business Machines Corporation
- Anne Gattiker
- G01 - MEASURING TESTING
Information Patent Grant
Designing scan chains with specific parameter sensitivities to iden...
- Patent number 7,194,706
- Issue date Mar 20, 2007
- International Business Machines Corporation
- James W. Adkisson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for defect evaluation using quiescent power plane...
- Patent number 7,127,690
- Issue date Oct 24, 2006
- International Business Machines Corporation
- Anne Elizabeth Gattiker
- G01 - MEASURING TESTING
Information Patent Grant
Defect diagnosis for semiconductor integrated circuits
- Patent number 7,089,514
- Issue date Aug 8, 2006
- International Business Machines Corporation
- James W. Adkisson
- G01 - MEASURING TESTING
Information Patent Grant
Functional pattern logic diagnostic method
- Patent number 7,017,095
- Issue date Mar 21, 2006
- International Business Machines Corporation
- Donato Forlenza
- G01 - MEASURING TESTING
Information Patent Grant
Stuck-at fault scan chain diagnostic method
- Patent number 7,010,735
- Issue date Mar 7, 2006
- International Business Machines Corporation
- Franco Motika
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for monitoring defects
- Patent number 6,998,866
- Issue date Feb 14, 2006
- International Business Machines Corporation
- Greg Bazan
- G01 - MEASURING TESTING
Information Patent Grant
Diagnostic method for structural scan chain designs
- Patent number 6,961,886
- Issue date Nov 1, 2005
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Grant
AC defect detection and failure avoidance power up and diagnostic s...
- Patent number 6,763,314
- Issue date Jul 13, 2004
- International Business Machines Corporation
- Phillip J. Nigh
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for determining repeatable yield detractors of in...
- Patent number 6,751,765
- Issue date Jun 15, 2004
- International Business Machines Corporation
- Richard F. Rizzolo
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit device defect detection method and apparatus emp...
- Patent number 6,650,130
- Issue date Nov 18, 2003
- International Business Machines Corporation
- Jeffrey A. Kash
- G01 - MEASURING TESTING
Information Patent Grant
Using time resolved light emission from VLSI circuit devices for na...
- Patent number 6,650,768
- Issue date Nov 18, 2003
- International Business Machines Corporation
- Richard James Evans
- G01 - MEASURING TESTING
Information Patent Grant
Method for test optimization using historical and actual fabricatio...
- Patent number 6,618,682
- Issue date Sep 9, 2003
- International Business Machines Corporation
- Raymond J. Bulaga
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
AC scan diagnostic method
- Patent number 6,516,432
- Issue date Feb 4, 2003
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Grant
Logic built-in self test selective signature generation
- Patent number 6,442,723
- Issue date Aug 27, 2002
- International Business Machines Corporation
- Timothy J. Koprowski
- G01 - MEASURING TESTING
Information Patent Grant
Using time resolved light emission from VLSI circuit devices for na...
- Patent number 6,304,668
- Issue date Oct 16, 2001
- International Business Machines Corporation
- Richard James Evans
Information Patent Grant
Testing method for dynamic logic keeper device
- Patent number 6,269,461
- Issue date Jul 31, 2001
- International Business Machines Corporation
- Robert Dean Adams
- G01 - MEASURING TESTING
Information Patent Grant
Method for identifying long paths in integrated circuits
- Patent number 6,125,461
- Issue date Sep 26, 2000
- International Business Machines Corporation
- Leendert Marinus Huisman
- G01 - MEASURING TESTING
Information Patent Grant
Built-in dynamic stress for integrated circuits
- Patent number 5,982,189
- Issue date Nov 9, 1999
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Grant
Electric field test of integrated circuit component
- Patent number 5,942,911
- Issue date Aug 24, 1999
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Grant
Logic built in self-test diagnostic method
- Patent number 5,930,270
- Issue date Jul 27, 1999
- International Business Machines Corporation
- Donato O. Forlenza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electric field test of integrated circuit component
- Patent number 5,807,763
- Issue date Sep 15, 1998
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
ONLINE MULTIPROCESSOR SYSTEM RELIABILITY DEFECT TESTING
- Publication number 20090241124
- Publication date Sep 24, 2009
- Monty M. Denneau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Testing Using Independently Controllable Voltage Islands
- Publication number 20080284459
- Publication date Nov 20, 2008
- International Business Machines Corporation
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION
- Publication number 20080211531
- Publication date Sep 4, 2008
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION
- Publication number 20080211530
- Publication date Sep 4, 2008
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION
- Publication number 20080036486
- Publication date Feb 14, 2008
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Application
Testing using independently controllable voltage islands
- Publication number 20060158222
- Publication date Jul 20, 2006
- Anne Gattiker
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit testing methods using well bias modification
- Publication number 20060071653
- Publication date Apr 6, 2006
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Application
DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS
- Publication number 20060036975
- Publication date Feb 16, 2006
- International Business Machines Corporation
- James W. Adkisson
- G01 - MEASURING TESTING
Information Patent Application
Designing Scan Chains With Specific Parameter Sensitivities to Iden...
- Publication number 20060026472
- Publication date Feb 2, 2006
- International Business Machines Corporation
- James W. Adkisson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT AND METHOD FOR MONITORING DEFECTS
- Publication number 20060022693
- Publication date Feb 2, 2006
- International Business Machines Corporation
- Greg Bazan
- G01 - MEASURING TESTING
Information Patent Application
Functional pattern logic diagnostic method
- Publication number 20050289426
- Publication date Dec 29, 2005
- Donato Forlenza
- G01 - MEASURING TESTING
Information Patent Application
Method and system for defect evaluation using quiescent power plane...
- Publication number 20050125711
- Publication date Jun 9, 2005
- International Business Machines Corporation
- Anne Elizabeth Gattiker
- G01 - MEASURING TESTING
Information Patent Application
DIAGNOSTIC METHOD FOR STRUCTURAL SCAN CHAIN DESIGNS
- Publication number 20040210808
- Publication date Oct 21, 2004
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Application
Functional pattern logic diagnostic method
- Publication number 20040010741
- Publication date Jan 15, 2004
- International Business Machines Corporation
- Donato Forlenza
- G01 - MEASURING TESTING
Information Patent Application
Stuck-at fault scan chain diagnostic method
- Publication number 20030131294
- Publication date Jul 10, 2003
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Application
AC defect detection and failure avoidance power up and diagnostic s...
- Publication number 20030065484
- Publication date Apr 3, 2003
- Phillip J. Nigh
- G01 - MEASURING TESTING
Information Patent Application
Method for test optimization using historical and actual fabricatio...
- Publication number 20020155628
- Publication date Oct 24, 2002
- International Business Machines Corporation
- Raymond J. Bulaga
- H01 - BASIC ELECTRIC ELEMENTS

Phillip J Nigh

Person

Patents Grantslast 30 patents

Online multiprocessor system reliability defect testing

Integrated circuit testing methods using well bias modification

Functional pattern logic diagnostic method

Integrated circuit testing methods using well bias modification

Integrated circuit testing method using well bias modification

Testing using independently controllable voltage islands

Integrated circuit testing methods using well bias modification

Designing scan chains with specific parameter sensitivities to iden...

Method and system for defect evaluation using quiescent power plane...

Defect diagnosis for semiconductor integrated circuits

Functional pattern logic diagnostic method

Stuck-at fault scan chain diagnostic method

Circuit and method for monitoring defects

Diagnostic method for structural scan chain designs

AC defect detection and failure avoidance power up and diagnostic s...

Method and system for determining repeatable yield detractors of in...

Integrated circuit device defect detection method and apparatus emp...

Using time resolved light emission from VLSI circuit devices for na...

Method for test optimization using historical and actual fabricatio...

AC scan diagnostic method

Logic built-in self test selective signature generation

Using time resolved light emission from VLSI circuit devices for na...

Testing method for dynamic logic keeper device

Method for identifying long paths in integrated circuits

Built-in dynamic stress for integrated circuits

Electric field test of integrated circuit component

Logic built in self-test diagnostic method

Electric field test of integrated circuit component

Patents Applicationslast 30 patents

ONLINE MULTIPROCESSOR SYSTEM RELIABILITY DEFECT TESTING

Testing Using Independently Controllable Voltage Islands

INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION

INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION

INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION

Testing using independently controllable voltage islands

Integrated circuit testing methods using well bias modification

DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS

Designing Scan Chains With Specific Parameter Sensitivities to Iden...

CIRCUIT AND METHOD FOR MONITORING DEFECTS

Functional pattern logic diagnostic method

Method and system for defect evaluation using quiescent power plane...

DIAGNOSTIC METHOD FOR STRUCTURAL SCAN CHAIN DESIGNS

Functional pattern logic diagnostic method

Stuck-at fault scan chain diagnostic method

AC defect detection and failure avoidance power up and diagnostic s...

Method for test optimization using historical and actual fabricatio...