PIDUGU L. NARAYANA

Person

SUNNYVALE, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configurage data setup/hold timing circuit with user programmable d...
- Patent number 6,907,539
- Issue date Jun 14, 2005
- Cypress Semiconductor Corp.
- Padma S. Nagarasa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed test architecture for multiport RAMs or other circuitry
- Patent number 6,675,336
- Issue date Jan 6, 2004
- Cypress Semiconductor Corp.
- Sangeeta Thakur
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, architecture and circuit for controlling and/or operating a...
- Patent number 6,628,171
- Issue date Sep 30, 2003
- Cypress Semiconductor Corp.
- Richard Chou
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Data packet transmission scheduling
- Patent number 6,577,635
- Issue date Jun 10, 2003
- Maple Optical Systems, Inc.
- Pidugu Narayana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fifo bus-sizing, bus-matching datapath architecture
- Patent number 6,526,470
- Issue date Feb 25, 2003
- Cypress Semiconductor Corp.
- Daniel Eric Cress
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits, architectures, and methods for generating a periodic sign...
- Patent number 6,489,805
- Issue date Dec 3, 2002
- Cypress Semiconductor Corp.
- Johnie Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data packet transmission scheduling using a partitioned heap
- Patent number 6,469,983
- Issue date Oct 22, 2002
- Maple Optical Systems, Inc.
- Pidugu Narayana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory architecture
- Patent number 6,400,642
- Issue date Jun 4, 2002
- Cypress Semiconductor Corp.
- Rakesh Mehrotra
- G11 - INFORMATION STORAGE
Information Patent Grant
Composite flag generation for DDR FIFOs
- Patent number 6,377,071
- Issue date Apr 23, 2002
- Cypress Semiconductor Corp.
- Bo Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for shorting retransmit recovery times utilizi...
- Patent number 6,366,979
- Issue date Apr 2, 2002
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Column redundancy scheme for bus-matching fifos
- Patent number 6,292,013
- Issue date Sep 18, 2001
- Cypress Semiconductor Corp.
- Daniel Eric Cress
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture
- Patent number 6,240,031
- Issue date May 29, 2001
- Cypress Semiconductor Corp.
- Rakesh Mehrotra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Oscillator circuit controlled by programmable logic
- Patent number 6,177,843
- Issue date Jan 23, 2001
- Cypress Semiconductor Corp.
- Richard Chou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for generating almost full and almost empty flags in respon...
- Patent number 6,070,203
- Issue date May 30, 2000
- Cypress Semiconductor Corp.
- Andrew L. Hawkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell
- Patent number 6,055,177
- Issue date Apr 25, 2000
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G11 - INFORMATION STORAGE
Information Patent Grant
Staggered bitline precharge scheme
- Patent number 6,023,435
- Issue date Feb 8, 2000
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G11 - INFORMATION STORAGE
Information Patent Grant
State machine design for generating empty and full flags in an asyn...
- Patent number 6,016,403
- Issue date Jan 18, 2000
- Cypress Semiconductor Corp.
- Andrew L. Hawkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Half-full flag generator for synchronous FIFOs
- Patent number 5,994,920
- Issue date Nov 30, 1999
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State machine design for generating half-full and half-empty flags...
- Patent number 5,991,834
- Issue date Nov 23, 1999
- Cypress Semiconductor Corp.
- Andrew L. Hawkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full and empty flag generator for synchronous FIFOs
- Patent number 5,963,056
- Issue date Oct 5, 1999
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal generation decoder circuit and method
- Patent number 5,955,897
- Issue date Sep 21, 1999
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed FIFO mark and retransmit scheme using latches and precharge
- Patent number 5,860,160
- Issue date Jan 12, 1999
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable read-write word line equality signal generation for FIFOs
- Patent number 5,852,748
- Issue date Dec 22, 1998
- Cypress Semiconductor Corp.
- Andrew L. Hawkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit having plurality of carry/sum adders having read count, wri...
- Patent number 5,850,568
- Issue date Dec 15, 1998
- Cypress Semiconductor Corporation
- Andrew L. Hawkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Half-full flag generator for synchronous FIFOs
- Patent number 5,844,423
- Issue date Dec 1, 1998
- Cypress Semiconductor Corporation
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State machine design for generating half-full and half-empty flags...
- Patent number 5,809,339
- Issue date Sep 15, 1998
- Cypress Semiconductor Corp.
- Andrew L. Hawkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State machine design for generating empty and full flags in an asyn...
- Patent number 5,712,992
- Issue date Jan 27, 1998
- Cypress Semiconductor Corporation
- Andrew L. Hawkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal generation decoder circuit and method
- Patent number 5,661,418
- Issue date Aug 26, 1997
- Cypress Semiconductor Corp.
- Pidugu L. Narayana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full and empty flag generator for synchronous FIFOS
- Patent number 5,627,797
- Issue date May 6, 1997
- Cypress Semiconductor Corporation
- Andrew L. Hawkins
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CIRCUITS, ARCHITECTURES, AND METHODS FOR GENERATING A PERIODIC SIGN...
- Publication number 20020171452
- Publication date Nov 21, 2002
- JOHNIE AU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Packet transmission scheduling in a data communication network
- Publication number 20020126690
- Publication date Sep 12, 2002
- Maple Optical Systems, Inc.
- Pidugu Narayana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Data packet transmission scheduling based on anticipated finish times
- Publication number 20020118706
- Publication date Aug 29, 2002
- Maple Optical Systems, Inc.
- Pidugu Narayana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DATA PACKET TRANSMISSION SCHEDULING USING A PARTITIONED HEAP
- Publication number 20020118645
- Publication date Aug 29, 2002
- Maple Optical Systems, Inc.
- Pidugu Narayana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Data packet transmission scheduling
- Publication number 20020118683
- Publication date Aug 29, 2002
- Maple Optical Systems, Inc.
- Pidugu Narayana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

PIDUGU L. NARAYANA

Person

Patents Grantslast 30 patents

Configurage data setup/hold timing circuit with user programmable d...

Distributed test architecture for multiport RAMs or other circuitry

Method, architecture and circuit for controlling and/or operating a...

Data packet transmission scheduling

Fifo bus-sizing, bus-matching datapath architecture

Circuits, architectures, and methods for generating a periodic sign...

Data packet transmission scheduling using a partitioned heap

Memory architecture

Composite flag generation for DDR FIFOs

Apparatus and method for shorting retransmit recovery times utilizi...

Column redundancy scheme for bus-matching fifos

Memory architecture

Oscillator circuit controlled by programmable logic

Circuit for generating almost full and almost empty flags in respon...

Memory cell

Staggered bitline precharge scheme

State machine design for generating empty and full flags in an asyn...

Half-full flag generator for synchronous FIFOs

State machine design for generating half-full and half-empty flags...

Full and empty flag generator for synchronous FIFOs

Signal generation decoder circuit and method

High speed FIFO mark and retransmit scheme using latches and precharge

Programmable read-write word line equality signal generation for FIFOs

Circuit having plurality of carry/sum adders having read count, wri...

Half-full flag generator for synchronous FIFOs

State machine design for generating half-full and half-empty flags...

State machine design for generating empty and full flags in an asyn...

Signal generation decoder circuit and method

Full and empty flag generator for synchronous FIFOS

Patents Applicationslast 30 patents

CIRCUITS, ARCHITECTURES, AND METHODS FOR GENERATING A PERIODIC SIGN...

Packet transmission scheduling in a data communication network

Data packet transmission scheduling based on anticipated finish times

DATA PACKET TRANSMISSION SCHEDULING USING A PARTITIONED HEAP

Data packet transmission scheduling