Prakash Narain

Person

San Carlos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for identifying integrated circuit failures caused by async...
- Patent number 10,935,595
- Issue date Mar 2, 2021
- Real Intent, Inc.
- Vishnu Vimjam
- G01 - MEASURING TESTING
Information Patent Grant
Methods for identifying integrated circuit failures caused by reset...
- Patent number 10,936,774
- Issue date Mar 2, 2021
- Real Intent, Inc.
- Oren Katzir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical functional verification
- Patent number 6,839,884
- Issue date Jan 4, 2005
- Real Intent, Inc.
- Prakash Narain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for characterizing information about design at...
- Patent number 6,704,912
- Issue date Mar 9, 2004
- Real Intent, Inc.
- Prakash Narain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intent-driven functional verification of digital designs
- Patent number 6,651,228
- Issue date Nov 18, 2003
- Real Intent, Inc.
- Prakash Narain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining dependency relationships among design verification checks
- Patent number 6,571,375
- Issue date May 27, 2003
- Real Intent, Inc.
- Prakash Narain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic formulation of design verification checks based upon a la...
- Patent number 6,539,523
- Issue date Mar 25, 2003
- Real Intent, Inc.
- Prakash Narain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling and verifying the intended flow of logical signals in a ha...
- Patent number 6,493,852
- Issue date Dec 10, 2002
- Real Intent, Inc.
- Prakash Narain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a testable high frequency synchronizer
- Patent number 5,987,081
- Issue date Nov 16, 1999
- Sun Microsystems, Inc.
- Michael A. Csoppenszky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing a circuit with reduced test patter...
- Patent number 5,740,182
- Issue date Apr 14, 1998
- Sun Microsystems, Inc.
- Prakash Narain
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Intent-driven functional verification of digital designs
- Publication number 20040117746
- Publication date Jun 17, 2004
- Prakash Narain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CHARACTERIZING INFORMATION ABOUT DESIGN AT...
- Publication number 20030229863
- Publication date Dec 11, 2003
- Prakash Narain
- G06 - COMPUTING CALCULATING COUNTING

Prakash Narain

Person

Patents Grantslast 30 patents

Methods for identifying integrated circuit failures caused by async...

Methods for identifying integrated circuit failures caused by reset...

Hierarchical functional verification

Method and apparatus for characterizing information about design at...

Intent-driven functional verification of digital designs

Determining dependency relationships among design verification checks

Automatic formulation of design verification checks based upon a la...

Modeling and verifying the intended flow of logical signals in a ha...

Method and apparatus for a testable high frequency synchronizer

Method and apparatus for testing a circuit with reduced test patter...

Patents Applicationslast 30 patents

Intent-driven functional verification of digital designs

METHOD AND APPARATUS FOR CHARACTERIZING INFORMATION ABOUT DESIGN AT...