Qi-Zong Hong

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Thin film resistor with punch-through vias
- Patent number 11,848,268
- Issue date Dec 19, 2023
- Texas Instruments Incorporated
- Dhishan Kande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC with thin film resistor with metal walls
- Patent number 11,424,183
- Issue date Aug 23, 2022
- Texas Instruments Incorporated
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin film resistor with punch-through vias
- Patent number 11,101,212
- Issue date Aug 24, 2021
- Texas Instruments Incorporated
- Dhishan Kande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC with thin film resistor with metal walls
- Patent number 10,784,193
- Issue date Sep 22, 2020
- Texas Instruments Incorporated
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-situ plasma treatment for thin film resistors
- Patent number 10,439,020
- Issue date Oct 8, 2019
- Texas Instruments Incorporated
- Abbas Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal interconnect processing for an integrated circuit metal stack
- Patent number 10,361,095
- Issue date Jul 23, 2019
- Texas Instruments Incorporated
- Abbas Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin film resistor with punch-through vias
- Patent number 10,354,951
- Issue date Jul 16, 2019
- Texas Instruments Incorporated
- Dhishan Kande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilevel via placement with improved yield in dual damascene inte...
- Patent number 10,242,147
- Issue date Mar 26, 2019
- Texas Instruments Incorporated
- Qi-Zhong Hong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for a thin film resistor using a via retardation...
- Patent number 10,211,278
- Issue date Feb 19, 2019
- Texas Instruments Incorporated
- Abbas Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal interconnect processing for a non-reactive metal stack
- Patent number 10,002,774
- Issue date Jun 19, 2018
- Texas Instruments Incorporated
- Abbas Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilevel via placement with improved yield in dual damascene inte...
- Patent number 9,589,093
- Issue date Mar 7, 2017
- Texas Instruments Incorporated
- Qi-Zhong Hong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of eliminating etch ridges in a dual damascene process
- Patent number 7,192,863
- Issue date Mar 20, 2007
- Texas Instruments Incorporated
- Lu Zhijian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System for improving thermal stability of copper damascene structure
- Patent number 6,903,000
- Issue date Jun 7, 2005
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor PMD layer dielectric
- Patent number 6,835,648
- Issue date Dec 28, 2004
- Texas Instruments Incorporated
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to improve silicide formation on polysilicon
- Patent number 6,777,300
- Issue date Aug 17, 2004
- Texas Instruments Incorporated
- Jorge Adrian Kittl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Si-rich surface layer capped diffusion barriers
- Patent number 6,680,249
- Issue date Jan 20, 2004
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating metal conductors and multi-level interconnec...
- Patent number 6,677,232
- Issue date Jan 13, 2004
- Texas Instruments Incorporated
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective aluminum plug formation and etchback process
- Patent number 6,660,650
- Issue date Dec 9, 2003
- Texas Instruments Incorporated
- Anthony J. Konecni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for isolating an exposed conducting surface
- Patent number 6,544,886
- Issue date Apr 8, 2003
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Yield improvement of dual damascene fabrication through oxide filling
- Patent number 6,461,955
- Issue date Oct 8, 2002
- Texas Instruments Incorporated
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a silicide layer using metallic impurities and pr...
- Patent number 6,372,566
- Issue date Apr 16, 2002
- Texas Instruments Incorporated
- Jorge A. Kittl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit interconnect and method
- Patent number 6,358,849
- Issue date Mar 19, 2002
- Texas Instruments Incorporated
- Robert H. Havemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Passivation of inlaid metallization
- Patent number 6,355,559
- Issue date Mar 12, 2002
- Texas Instruments Incorporated
- Robert H. Havemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of improving the texture of aluminum metallization for tungs...
- Patent number 6,329,282
- Issue date Dec 11, 2001
- Texas Instruments Incorporated
- Wei-Yung Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced temperature contact/via filling
- Patent number 6,323,553
- Issue date Nov 27, 2001
- Texas Instrument Incorporated
- Wei-Yung Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming diffusion barriers for copper metallization in in...
- Patent number 6,245,672
- Issue date Jun 12, 2001
- Texas Instruments Incorporated
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-stage semiconductor cavity filling process
- Patent number 6,150,252
- Issue date Nov 21, 2000
- Texas Instruments Incorporated
- Wei-Yung Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced temperature contact/via filling
- Patent number 6,143,645
- Issue date Nov 7, 2000
- Texas Instruments Incorporated
- Wei-Yung Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
TiN+Al films and processes
- Patent number 6,120,842
- Issue date Sep 19, 2000
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface protective layer for improved silicide formation
- Patent number 6,114,733
- Issue date Sep 5, 2000
- Texas Instruments Incorporated
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DUAL RESISTOR INTEGRATION
- Publication number 20230154915
- Publication date May 18, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Bhaskar Srinivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN FILM RESISTOR WITH PUNCH-THROUGH VIAS
- Publication number 20210343642
- Publication date Nov 4, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Dhishan Kande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC WITH THIN FILM RESISTOR WITH METAL WALLS
- Publication number 20200381358
- Publication date Dec 3, 2020
- TEXAS INSTRUMENTS INCORPORATED
- QI-ZHONG HONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC WITH THIN FILM RESISTOR WITH METAL WALLS
- Publication number 20200035598
- Publication date Jan 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- QI-ZHONG HONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN FILM RESISTOR WITH PUNCH-THROUGH VIAS
- Publication number 20190295948
- Publication date Sep 26, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Dhishan Kande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN FILM RESISTOR WITH PUNCH-THROUGH VIAS
- Publication number 20190221516
- Publication date Jul 18, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Dhishan Kande
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-SITU PLASMA TREATMENT FOR THIN FILM RESISTORS
- Publication number 20190198603
- Publication date Jun 27, 2019
- TEXAS INSTRUMENTS INCORPORATED
- ABBAS ALI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH VOLTAGE CAPACITORS AND METHODS OF MANUFACTURING THE SAME
- Publication number 20190108943
- Publication date Apr 11, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Gang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL INTERCONNECT PROCESSING FOR AN INTEGRATED CIRCUIT METAL STACK
- Publication number 20190074193
- Publication date Mar 7, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Abbas ALI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE AND METHOD FOR A THIN FILM RESISTOR USING A VIA RETARDATION...
- Publication number 20190019858
- Publication date Jan 17, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Abbas Ali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTILEVEL VIA PLACEMENT WITH IMPROVED YIELD IN DUAL DAMASCENE INTE...
- Publication number 20170177783
- Publication date Jun 22, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Qi-Zhong HONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTILEVEL VIA PLACEMENT WITH IMPROVED YIELD IN DUAL DAMASCENE INTE...
- Publication number 20150186588
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Qi-Zhong HONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Plasma Treatment of an Etch Stop Layer
- Publication number 20060194447
- Publication date Aug 31, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Ju-Ai Ruan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Plasma treatment of an etch stop layer
- Publication number 20060081965
- Publication date Apr 20, 2006
- Ju-Ai Ruan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of eliminating etch ridges in a dual damascene process
- Publication number 20060024956
- Publication date Feb 2, 2006
- Lu Zhijian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System for improving thermal stability of copper damascene structure
- Publication number 20050186788
- Publication date Aug 25, 2005
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit capacitor in multi-level metallization
- Publication number 20050048762
- Publication date Mar 3, 2005
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PMD LAYER DIELECTRIC
- Publication number 20040238853
- Publication date Dec 2, 2004
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System for improving thermal stability of copper damascene structure
- Publication number 20030124828
- Publication date Jul 3, 2003
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Si-rich surface layer capped diffusion barriers
- Publication number 20020192950
- Publication date Dec 19, 2002
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Si-rich surface layer capped diffusion barriers
- Publication number 20020180044
- Publication date Dec 5, 2002
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to improve silicide formation on polysilicon
- Publication number 20020086485
- Publication date Jul 4, 2002
- Jorge Adrian Kittl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for isolating an exposed conducting surface
- Publication number 20020086522
- Publication date Jul 4, 2002
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating metal conductors and multi-level interconnec...
- Publication number 20020081837
- Publication date Jun 27, 2002
- Qi-Zhong Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SILICIDE LAYER USING METALLIC IMPURITIES AND PR...
- Publication number 20020045307
- Publication date Apr 18, 2002
- JORGE KITTL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USING AN ELEVATED SILICIDE AS DIFFUSION SOURCE FOR DEEP SUB-MICRON...
- Publication number 20010038131
- Publication date Nov 8, 2001
- JERRY CHE-JEN HU
- H01 - BASIC ELECTRIC ELEMENTS

Qi-Zong Hong

Person

Patents Grantslast 30 patents

Thin film resistor with punch-through vias

IC with thin film resistor with metal walls

Thin film resistor with punch-through vias

IC with thin film resistor with metal walls

In-situ plasma treatment for thin film resistors

Metal interconnect processing for an integrated circuit metal stack

Thin film resistor with punch-through vias

Multilevel via placement with improved yield in dual damascene inte...

Device and method for a thin film resistor using a via retardation...

Metal interconnect processing for a non-reactive metal stack

Multilevel via placement with improved yield in dual damascene inte...

Method of eliminating etch ridges in a dual damascene process

System for improving thermal stability of copper damascene structure

Semiconductor PMD layer dielectric

Method to improve silicide formation on polysilicon

Si-rich surface layer capped diffusion barriers

Method for fabricating metal conductors and multi-level interconnec...

Selective aluminum plug formation and etchback process

Process for isolating an exposed conducting surface

Yield improvement of dual damascene fabrication through oxide filling

Method of forming a silicide layer using metallic impurities and pr...

Integrated circuit interconnect and method

Passivation of inlaid metallization

Method of improving the texture of aluminum metallization for tungs...

Reduced temperature contact/via filling

Method of forming diffusion barriers for copper metallization in in...

Multi-stage semiconductor cavity filling process

Reduced temperature contact/via filling

TiN+Al films and processes

Surface protective layer for improved silicide formation

Patents Applicationslast 30 patents

DUAL RESISTOR INTEGRATION

THIN FILM RESISTOR WITH PUNCH-THROUGH VIAS

IC WITH THIN FILM RESISTOR WITH METAL WALLS

IC WITH THIN FILM RESISTOR WITH METAL WALLS

THIN FILM RESISTOR WITH PUNCH-THROUGH VIAS

THIN FILM RESISTOR WITH PUNCH-THROUGH VIAS

IN-SITU PLASMA TREATMENT FOR THIN FILM RESISTORS

HIGH VOLTAGE CAPACITORS AND METHODS OF MANUFACTURING THE SAME

METAL INTERCONNECT PROCESSING FOR AN INTEGRATED CIRCUIT METAL STACK

DEVICE AND METHOD FOR A THIN FILM RESISTOR USING A VIA RETARDATION...

MULTILEVEL VIA PLACEMENT WITH IMPROVED YIELD IN DUAL DAMASCENE INTE...

MULTILEVEL VIA PLACEMENT WITH IMPROVED YIELD IN DUAL DAMASCENE INTE...

Plasma Treatment of an Etch Stop Layer

Plasma treatment of an etch stop layer

Method of eliminating etch ridges in a dual damascene process

System for improving thermal stability of copper damascene structure

Integrated circuit capacitor in multi-level metallization

SEMICONDUCTOR PMD LAYER DIELECTRIC

System for improving thermal stability of copper damascene structure

Si-rich surface layer capped diffusion barriers

Si-rich surface layer capped diffusion barriers

Method to improve silicide formation on polysilicon

Process for isolating an exposed conducting surface

Method for fabricating metal conductors and multi-level interconnec...

METHOD OF FORMING A SILICIDE LAYER USING METALLIC IMPURITIES AND PR...

USING AN ELEVATED SILICIDE AS DIFFUSION SOURCE FOR DEEP SUB-MICRON...