Randall Cher Liang Cha

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with self-aligned line and via
- Patent number 8,766,454
- Issue date Jul 1, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to pattern small features by using a re-flowable hard mask
- Patent number 6,828,082
- Issue date Dec 7, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate elevated source/drain transistor with large are...
- Patent number 6,780,691
- Issue date Aug 24, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate elevated source/drain structures in MOS transis...
- Patent number 6,727,151
- Issue date Apr 27, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Yung Fu Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate a single gate with dual work-functions
- Patent number 6,664,153
- Issue date Dec 16, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating variable length vertical transistors
- Patent number 6,632,712
- Issue date Oct 14, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating SOI devices with option of incorporating air...
- Patent number 6,613,652
- Issue date Sep 2, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming small transistor gates by using self-aligned reve...
- Patent number 6,610,604
- Issue date Aug 26, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicon-on-insulator device wafer die
- Patent number 6,558,994
- Issue date May 6, 2003
- Chartered Semiconductors Maufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form an asymmetrical non-volatile memory device using sma...
- Patent number 6,544,848
- Issue date Apr 8, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Salicide method for producing a semiconductor device using silicon/...
- Patent number 6,534,390
- Issue date Mar 18, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Yung Fu Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate dish-free copper interconnects
- Patent number 6,531,386
- Issue date Mar 11, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng-Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assorted aluminum wiring design to enhance chip-level performance f...
- Patent number 6,472,697
- Issue date Oct 29, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating CMOS device with dual gate electrode
- Patent number 6,468,851
- Issue date Oct 22, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating complementary silicon on insulator devices u...
- Patent number 6,468,880
- Issue date Oct 22, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified method to reduce or eliminate STI oxide divots
- Patent number 6,432,797
- Issue date Aug 13, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form high k dielectric and silicide to reduce poly deplet...
- Patent number 6,429,109
- Issue date Aug 6, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Jia Zhen Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assorted aluminum wiring design to enhance chip-level performance f...
- Patent number 6,399,471
- Issue date Jun 4, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate RF inductors with minimum area
- Patent number 6,387,747
- Issue date May 14, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to reduce polysilicon depletion in MOS transistors
- Patent number 6,387,784
- Issue date May 14, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yung Fu Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-leakage DRAM structures using selective silicon epitaxial growt...
- Patent number 6,384,437
- Issue date May 7, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Kheng Chok Tee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Effective retardation of fluorine radical attack on metal lines via...
- Patent number 6,376,360
- Issue date Apr 23, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Versatile copper-wiring layout design with low-k dielectric integra...
- Patent number 6,355,563
- Issue date Mar 12, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for a short channel CMOS transistor with small overlay capac...
- Patent number 6,348,385
- Issue date Feb 19, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to eliminate top metal corner shaping during bottom metal pa...
- Patent number 6,319,767
- Issue date Nov 20, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making low-leakage DRAM structures using selective silic...
- Patent number 6,319,772
- Issue date Nov 20, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Kheng Chok Tee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to eliminate top metal corner shaping during bottom metal pa...
- Patent number 6,284,590
- Issue date Sep 4, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to reduce compressive stress in the silicon substrate during...
- Patent number 6,284,610
- Issue date Sep 4, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT WITH SELF-ALIGNED LINE AND VIA
- Publication number 20070075371
- Publication date Apr 5, 2007
- Chartered Semiconductor Manufacturing LTD.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to produce dual gates (one metal and one poly or metal silic...
- Publication number 20050101083
- Publication date May 12, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Chew Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to pattern small features by using a re-flowable hard mask
- Publication number 20050089777
- Publication date Apr 28, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to fabricate elevated source/drain transistor with large are...
- Publication number 20040033668
- Publication date Feb 19, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FABRICATE ELEVATED SOURCE/DRAIN STRUCTURES IN MOS TRANSIS...
- Publication number 20040029320
- Publication date Feb 12, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Yung Fu Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with self-aligned line and via and manufacturing...
- Publication number 20030197279
- Publication date Oct 23, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to pattern small features by using a re-flowable hard mask
- Publication number 20030152871
- Publication date Aug 14, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to fabricate a single gate with dual work-functions
- Publication number 20030153139
- Publication date Aug 14, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SMALL TRANSISTOR GATES BY USING SELF-ALIGNED REVE...
- Publication number 20030148617
- Publication date Aug 7, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual silicon-on-insulator device wafer die
- Publication number 20030107083
- Publication date Jun 12, 2003
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating SOI devices with option of incorporating air...
- Publication number 20020132448
- Publication date Sep 19, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Assorted aluminum wiring design to enhance chip-level performance f...
- Publication number 20020127834
- Publication date Sep 12, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel technique to achieve thick silicide film for ultra-shallow ju...
- Publication number 20020102802
- Publication date Aug 1, 2002
- Cheng Cheh Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIMPLIFIED METHOD TO REDUCE OR ELIMINATE STI OXIDE DIVOTS
- Publication number 20020098661
- Publication date Jul 25, 2002
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-LEAKAGE DRAM STRUCTURES USING SELECTIVE SILICON EPITAXIAL GROWT...
- Publication number 20020052077
- Publication date May 2, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Kheng Chok Tee
- H01 - BASIC ELECTRIC ELEMENTS

Randall Cher Liang Cha

Person

Patents Grantslast 30 patents

Integrated circuit with self-aligned line and via

Method to pattern small features by using a re-flowable hard mask

Method to fabricate elevated source/drain transistor with large are...

Method to fabricate elevated source/drain structures in MOS transis...

Method to fabricate a single gate with dual work-functions

Method of fabricating variable length vertical transistors

Method for fabricating SOI devices with option of incorporating air...

Method of forming small transistor gates by using self-aligned reve...

Dual silicon-on-insulator device wafer die

Method to form an asymmetrical non-volatile memory device using sma...

Salicide method for producing a semiconductor device using silicon/...

Method to fabricate dish-free copper interconnects

Assorted aluminum wiring design to enhance chip-level performance f...

Method of fabricating CMOS device with dual gate electrode

Method for fabricating complementary silicon on insulator devices u...

Simplified method to reduce or eliminate STI oxide divots

Method to form high k dielectric and silicide to reduce poly deplet...

Assorted aluminum wiring design to enhance chip-level performance f...

Method to fabricate RF inductors with minimum area

Method to reduce polysilicon depletion in MOS transistors

Low-leakage DRAM structures using selective silicon epitaxial growt...

Effective retardation of fluorine radical attack on metal lines via...

Versatile copper-wiring layout design with low-k dielectric integra...

Method for a short channel CMOS transistor with small overlay capac...

Method to eliminate top metal corner shaping during bottom metal pa...

Method for making low-leakage DRAM structures using selective silic...

Method to eliminate top metal corner shaping during bottom metal pa...

Method to reduce compressive stress in the silicon substrate during...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT WITH SELF-ALIGNED LINE AND VIA

Method to produce dual gates (one metal and one poly or metal silic...

Method to pattern small features by using a re-flowable hard mask

Method to fabricate elevated source/drain transistor with large are...

METHOD TO FABRICATE ELEVATED SOURCE/DRAIN STRUCTURES IN MOS TRANSIS...

Integrated circuit with self-aligned line and via and manufacturing...

Method to pattern small features by using a re-flowable hard mask

Method to fabricate a single gate with dual work-functions

METHOD OF FORMING SMALL TRANSISTOR GATES BY USING SELF-ALIGNED REVE...

Dual silicon-on-insulator device wafer die

Method for fabricating SOI devices with option of incorporating air...

Assorted aluminum wiring design to enhance chip-level performance f...

Novel technique to achieve thick silicide film for ultra-shallow ju...

SIMPLIFIED METHOD TO REDUCE OR ELIMINATE STI OXIDE DIVOTS

LOW-LEAKAGE DRAM STRUCTURES USING SELECTIVE SILICON EPITAXIAL GROWT...