Raul Enriquez Shibayama

Person

Zapopan, MX

People

Patents Grantslast 30 patents

Information Patent Grant
High speed differential pinout arrangement including a power pin
- Patent number 11,990,709
- Issue date May 21, 2024
- Intel Corporation
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic on-die termination
- Patent number 10,812,075
- Issue date Oct 20, 2020
- Intel Corporation
- Harry Muljono
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method including a bridge device for interfa...
- Patent number 10,477,684
- Issue date Nov 12, 2019
- Intel Corporation
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Compact via structures and method of making same
- Patent number 10,249,924
- Issue date Apr 2, 2019
- Intel Corporation
- Kai Xiao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Hardware interface with space-efficient cell pattern
- Patent number 9,955,605
- Issue date Apr 24, 2018
- Intel Corporation
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Improving signaling performance in connector design
- Patent number 9,787,028
- Issue date Oct 10, 2017
- Intel Corporation
- Raul Enriquez-Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect arrangement for hexagonal attachment configurations
- Patent number 9,589,919
- Issue date Mar 7, 2017
- Intel Corporation
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit component bridge device
- Patent number 9,504,159
- Issue date Nov 22, 2016
- Intel Corporation
- Beom-Taek Lee
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Broadside coupled differential transmission lines having alternatin...
- Patent number 9,338,882
- Issue date May 10, 2016
- Intel Corporation
- Kai Xiao
- B33 - ADDITIVE MANUFACTURING TECHNOLOGY
Information Patent Grant
Crosstalk reduction in signal lines by crosstalk introduction
- Patent number 9,337,521
- Issue date May 10, 2016
- Intel Corporation
- Raul Enriquez Shibayama
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus for differential far-end crosstalk reduction
- Patent number 9,113,555
- Issue date Aug 18, 2015
- Intel Corporation
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
SOCKET INTERCONNECT STRUCTURES AND RELATED METHODS
- Publication number 20240113479
- Publication date Apr 4, 2024
- Intel Corporation
- Kai Xiao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPRESSED PINOUTS FOR HIGH-SPEED DIFFERENTIAL PAIRS
- Publication number 20230380067
- Publication date Nov 23, 2023
- Intel Corporation
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MICROSTRIP ROUTING CIRCUITS WITH DIELECTRIC FILMS
- Publication number 20230371172
- Publication date Nov 16, 2023
- Intel Corporation
- Alberto Carrillo Vazquez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH SPEED DIFFERENTIAL PINOUT ARRANGEMENT INCLUDING A POWER PIN
- Publication number 20210391671
- Publication date Dec 16, 2021
- Intel Corporation
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL ROUTING COMPONENT LAYOUT FOR CROSSTALK REDUCTION
- Publication number 20200083155
- Publication date Mar 12, 2020
- Intel Corporation
- Raul ENRIQUEZ SHIBAYAMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC ON-DIE TERMINATION
- Publication number 20190280691
- Publication date Sep 12, 2019
- Intel Corporation
- Harry Muljono
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIFFERENTIAL VIA WITH PER-LAYER VOID
- Publication number 20190116668
- Publication date Apr 18, 2019
- Intel Corporation
- Carlos Alberto Lizalde Moreno
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE INTERFACE WITH SPACE-EFFICIENT CELL PATTERN
- Publication number 20170288327
- Publication date Oct 5, 2017
- Intel Corporation
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ATTACHMENT TECHNIQUES FOR PRINTED CIRCUIT BOARDS
- Publication number 20170179625
- Publication date Jun 22, 2017
- Kai Xiao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE DEVICE FOR INTERFACING A PACKAGED DEVICE WITH A SUBSTRATE
- Publication number 20170094791
- Publication date Mar 30, 2017
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SYSTEM, APPARATUS AND METHOD FOR INTERCONNECTING CIRCUIT BOARDS
- Publication number 20170079140
- Publication date Mar 16, 2017
- Intel Corporation
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
COMPACT VIA STRUCTURES AND METHOD OF MAKING SAME
- Publication number 20160378215
- Publication date Dec 29, 2016
- Intel Corporation
- Kai Xiao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BROADSIDE COUPLED DIFFERENTIAL DESIGN
- Publication number 20150333387
- Publication date Nov 19, 2015
- KAI XIAO
- B33 - ADDITIVE MANUFACTURING TECHNOLOGY
Information Patent Application
CIRCUIT COMPONENT BRIDGE DEVICE
- Publication number 20150223336
- Publication date Aug 6, 2015
- Intel Corporation
- Beom-Taek Lee
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CROSSTALK REDUCTION IN SIGNAL LINES BY CROSSTALK INTRODUCTION
- Publication number 20150130553
- Publication date May 14, 2015
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reducing Far End Crosstalk in Single Ended Interconnects and Buses
- Publication number 20150085458
- Publication date Mar 26, 2015
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Apparatus for Differential Far-End Crosstalk Reduction
- Publication number 20140179162
- Publication date Jun 26, 2014
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and Apparatus for Far End Crosstalk Reduction in Single Ende...
- Publication number 20140174812
- Publication date Jun 26, 2014
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
IMPROVING SIGNALING PERFORMANCE IN CONNECTOR DESIGN
- Publication number 20140162498
- Publication date Jun 12, 2014
- Raul Enriquez-Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT ARRANGEMENT FOR HEXAGONAL ATTACHMENT CONFIGURATIONS
- Publication number 20140140027
- Publication date May 22, 2014
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS

Raul Enriquez Shibayama

Person

Patents Grantslast 30 patents

High speed differential pinout arrangement including a power pin

Dynamic on-die termination

Apparatus, system, and method including a bridge device for interfa...

Compact via structures and method of making same

Hardware interface with space-efficient cell pattern

Improving signaling performance in connector design

Interconnect arrangement for hexagonal attachment configurations

Circuit component bridge device

Broadside coupled differential transmission lines having alternatin...

Crosstalk reduction in signal lines by crosstalk introduction

Apparatus for differential far-end crosstalk reduction

Patents Applicationslast 30 patents

SOCKET INTERCONNECT STRUCTURES AND RELATED METHODS

COMPRESSED PINOUTS FOR HIGH-SPEED DIFFERENTIAL PAIRS

MICROSTRIP ROUTING CIRCUITS WITH DIELECTRIC FILMS

HIGH SPEED DIFFERENTIAL PINOUT ARRANGEMENT INCLUDING A POWER PIN

ELECTRICAL ROUTING COMPONENT LAYOUT FOR CROSSTALK REDUCTION

DYNAMIC ON-DIE TERMINATION

DIFFERENTIAL VIA WITH PER-LAYER VOID

HARDWARE INTERFACE WITH SPACE-EFFICIENT CELL PATTERN

ATTACHMENT TECHNIQUES FOR PRINTED CIRCUIT BOARDS

BRIDGE DEVICE FOR INTERFACING A PACKAGED DEVICE WITH A SUBSTRATE

SYSTEM, APPARATUS AND METHOD FOR INTERCONNECTING CIRCUIT BOARDS

COMPACT VIA STRUCTURES AND METHOD OF MAKING SAME

BROADSIDE COUPLED DIFFERENTIAL DESIGN

CIRCUIT COMPONENT BRIDGE DEVICE

CROSSTALK REDUCTION IN SIGNAL LINES BY CROSSTALK INTRODUCTION

Reducing Far End Crosstalk in Single Ended Interconnects and Buses

Apparatus for Differential Far-End Crosstalk Reduction

Method and Apparatus for Far End Crosstalk Reduction in Single Ende...

IMPROVING SIGNALING PERFORMANCE IN CONNECTOR DESIGN

INTERCONNECT ARRANGEMENT FOR HEXAGONAL ATTACHMENT CONFIGURATIONS