Ravi Sunkavalli

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data formatter for convolution
- Patent number 11,194,490
- Issue date Dec 7, 2021
- Xilinx, Inc.
- Ravi Sunkavalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically reconfigurable networking using a programmable integrat...
- Patent number 10,990,547
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Customizable multi queue DMA interface
- Patent number 10,983,920
- Issue date Apr 20, 2021
- Xilinx, Inc.
- Chandrasekhar S Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming platform architecture for inter-kernel circuit communicat...
- Patent number 10,725,942
- Issue date Jul 28, 2020
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cryptographic system
- Patent number 10,659,437
- Issue date May 19, 2020
- Xilinx, Inc.
- Ravi Sunkavalli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hierarchical global clock tree
- Patent number 8,933,734
- Issue date Jan 13, 2015
- Achronix Semiconductor Corporation
- Ravi Sunkavalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of signal processing engines with programmable lo...
- Patent number 8,700,837
- Issue date Apr 15, 2014
- Agate Logic, Inc.
- Hare Krishna Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical global clock tree
- Patent number 8,638,138
- Issue date Jan 28, 2014
- Achronix Semiconductor Corporation
- Ravi Sunkavalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic systems and methods employing configurable float...
- Patent number 8,429,214
- Issue date Apr 23, 2013
- Agate Logic, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reset signal distribution
- Patent number 8,305,124
- Issue date Nov 6, 2012
- Achronix Semiconductor Corporation
- Ravi Kurlagunda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Source-synchronous clocking
- Patent number 8,228,101
- Issue date Jul 24, 2012
- Achronix Semiconductor Corporation
- Rahul Nimaiyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of signal processing engines with programmable lo...
- Patent number 8,131,909
- Issue date Mar 6, 2012
- Agate Logic, Inc.
- Hare Krishna Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reset signal distribution
- Patent number 8,072,250
- Issue date Dec 6, 2011
- Achronix Semiconductor Corporation
- Ravi Kurlagunda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of configurable bus-based dedicated connection ci...
- Patent number 7,970,979
- Issue date Jun 28, 2011
- Agate Logic, Inc.
- Hare Krishna Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated logic cells employing configurable logic and dedicated lo...
- Patent number 7,836,113
- Issue date Nov 16, 2010
- Agate Logic, Inc.
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic systems and methods employing configurable float...
- Patent number 7,814,136
- Issue date Oct 12, 2010
- Agate Logic, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic cells with local connections
- Patent number 7,728,623
- Issue date Jun 1, 2010
- Agate Logic, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic cells with local connections
- Patent number 7,605,605
- Issue date Oct 20, 2009
- Cswitch Corporation
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated logic cells employing configurable logic and dedicated lo...
- Patent number 7,439,768
- Issue date Oct 21, 2008
- Cswitch Corporation
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile multiplexer-structures in programmable logic using serial...
- Patent number 7,428,722
- Issue date Sep 23, 2008
- Cswitch Corporation
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated logic cells employing sequential logic and control logic...
- Patent number 7,417,456
- Issue date Aug 26, 2008
- Cswitch Corporation
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated logic cells employing configurable logic and dedicated lo...
- Patent number 7,414,431
- Issue date Aug 19, 2008
- Cswitch Corporation
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated logic cells employing sequential logic and control logic...
- Patent number 7,414,432
- Issue date Aug 19, 2008
- Cswitch Corporation
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated logic cells employing sequential logic and control logic...
- Patent number 7,368,941
- Issue date May 6, 2008
- Cswitch Corporation
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dedicated logic cells employing configurable logic and dedicated lo...
- Patent number 7,358,765
- Issue date Apr 15, 2008
- Cswitch Corporation
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile multiplexer-structures in programmable logic using serial...
- Patent number 7,358,761
- Issue date Apr 15, 2008
- Csitch Corporation
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic and routing blocks with dedicated lines
- Patent number 7,176,717
- Issue date Feb 13, 2007
- Velogix, Inc.
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Simultaneous formation of charge storage and bitline to wordline is...
- Patent number 6,555,436
- Issue date Apr 29, 2003
- Advanced Micro Devices, Inc.
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar structure for non-volatile memory devices
- Patent number 6,541,816
- Issue date Apr 1, 2003
- Advanced Micro Devices, Inc.
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single bit array edges
- Patent number 6,493,261
- Issue date Dec 10, 2002
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMICALLY RECONFIGURABLE NETWORKING USING A PROGRAMMABLE INTEGRAT...
- Publication number 20210042252
- Publication date Feb 11, 2021
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING PLATFORM ARCHITECTURE FOR INTER-KERNEL CIRCUIT COMMUNICAT...
- Publication number 20200151120
- Publication date May 14, 2020
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRYPTOGRAPHIC SYSTEM
- Publication number 20200143088
- Publication date May 7, 2020
- Xilinx, Inc.
- Ravi Sunkavalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CUSTOMIZABLE MULTI QUEUE DMA INTERFACE
- Publication number 20190243781
- Publication date Aug 8, 2019
- Xilinx, Inc.
- Chandrasekhar S Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL GLOBAL CLOCK TREE
- Publication number 20140201560
- Publication date Jul 17, 2014
- Achronix Semiconductor Corporation
- Ravi Sunkavalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESET SIGNAL DISTRIBUTION
- Publication number 20120074991
- Publication date Mar 29, 2012
- Ravi Kurlagunda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL GLOBAL CLOCK TREE
- Publication number 20110063000
- Publication date Mar 17, 2011
- Ravi Sunkavalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOURCE-SYNCHRONOUS CLOCKING
- Publication number 20110062999
- Publication date Mar 17, 2011
- Rahul Nimaiyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESET SIGNAL DISTRIBUTION
- Publication number 20110062997
- Publication date Mar 17, 2011
- Ravi Kurlagunda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Logic Systems and Methods Employing Configurable Float...
- Publication number 20110010406
- Publication date Jan 13, 2011
- AGATE LOGIC, INC.
- Hare K. Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Versatile multiplexer-structures in programmable logic using serial...
- Publication number 20080129334
- Publication date Jun 5, 2008
- Cswitch Corporation
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable Logic Cells with Local Connections
- Publication number 20070085564
- Publication date Apr 19, 2007
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dedicated Logic Cells Employing Configurable Logic and Dedicated Lo...
- Publication number 20070085565
- Publication date Apr 19, 2007
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dedicated Logic Cells Employing Sequential Logic and Contol Logic F...
- Publication number 20070080711
- Publication date Apr 12, 2007
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dedicated Logic Cells Employing Configurable Logic and Dedicated Lo...
- Publication number 20070075740
- Publication date Apr 5, 2007
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dedicated Logic Cells Employing Configurable Logic and Dedicated Lo...
- Publication number 20070075739
- Publication date Apr 5, 2007
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dedicated Logic Cells Employing Sequential Logic and Control Logic...
- Publication number 20070075741
- Publication date Apr 5, 2007
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dedicated logic cells employing sequential logic and control logic...
- Publication number 20060186918
- Publication date Aug 24, 2006
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dedicated logic cells employing configurable logic and dedicated lo...
- Publication number 20060186919
- Publication date Aug 24, 2006
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic cells with Local Connections
- Publication number 20060164120
- Publication date Jul 27, 2006
- Flexlogics, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic and routing blocks with dedicated lines
- Publication number 20060158219
- Publication date Jul 20, 2006
- Flexlogics, Inc.
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Simultaneous formation of charge storage and bitline to wordline is...
- Publication number 20020192910
- Publication date Dec 19, 2002
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Planar structure for non-volatile memory devices
- Publication number 20020063277
- Publication date May 30, 2002
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS

Ravi Sunkavalli

Person

Patents Grantslast 30 patents

Data formatter for convolution

Dynamically reconfigurable networking using a programmable integrat...

Customizable multi queue DMA interface

Streaming platform architecture for inter-kernel circuit communicat...

Cryptographic system

Hierarchical global clock tree

System and method of signal processing engines with programmable lo...

Hierarchical global clock tree

Programmable logic systems and methods employing configurable float...

Reset signal distribution

Source-synchronous clocking

System and method of signal processing engines with programmable lo...

Reset signal distribution

System and method of configurable bus-based dedicated connection ci...

Dedicated logic cells employing configurable logic and dedicated lo...

Programmable logic systems and methods employing configurable float...

Programmable logic cells with local connections

Programmable logic cells with local connections

Dedicated logic cells employing configurable logic and dedicated lo...

Versatile multiplexer-structures in programmable logic using serial...

Dedicated logic cells employing sequential logic and control logic...

Dedicated logic cells employing configurable logic and dedicated lo...

Dedicated logic cells employing sequential logic and control logic...

Dedicated logic cells employing sequential logic and control logic...

Dedicated logic cells employing configurable logic and dedicated lo...

Versatile multiplexer-structures in programmable logic using serial...

Programmable logic and routing blocks with dedicated lines

Simultaneous formation of charge storage and bitline to wordline is...

Planar structure for non-volatile memory devices

Single bit array edges

Patents Applicationslast 30 patents

DYNAMICALLY RECONFIGURABLE NETWORKING USING A PROGRAMMABLE INTEGRAT...

STREAMING PLATFORM ARCHITECTURE FOR INTER-KERNEL CIRCUIT COMMUNICAT...

CRYPTOGRAPHIC SYSTEM

CUSTOMIZABLE MULTI QUEUE DMA INTERFACE

HIERARCHICAL GLOBAL CLOCK TREE

RESET SIGNAL DISTRIBUTION

HIERARCHICAL GLOBAL CLOCK TREE

SOURCE-SYNCHRONOUS CLOCKING

RESET SIGNAL DISTRIBUTION

Programmable Logic Systems and Methods Employing Configurable Float...

Versatile multiplexer-structures in programmable logic using serial...

Programmable Logic Cells with Local Connections

Dedicated Logic Cells Employing Configurable Logic and Dedicated Lo...

Dedicated Logic Cells Employing Sequential Logic and Contol Logic F...

Dedicated Logic Cells Employing Configurable Logic and Dedicated Lo...

Dedicated Logic Cells Employing Configurable Logic and Dedicated Lo...

Dedicated Logic Cells Employing Sequential Logic and Control Logic...

Dedicated logic cells employing sequential logic and control logic...

Dedicated logic cells employing configurable logic and dedicated lo...

Programmable logic cells with Local Connections

Programmable logic and routing blocks with dedicated lines

Simultaneous formation of charge storage and bitline to wordline is...

Planar structure for non-volatile memory devices