Ravishankar Sundaresan

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sram cell fabrication with interlevel Dielectric planarization
- Patent number RE41670
- Issue date Sep 14, 2010
- STMicroelectronics, Inc.
- Loi Nguyen
- 257 - Active solid-state devices
Information Patent Grant
Method and interlevel dielectric structure for improved metal step...
- Patent number 6,812,142
- Issue date Nov 2, 2004
- STMicroelectronics, Inc.
- Loi Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a one-sided polysilicon thin film transistor
- Patent number 6,753,576
- Issue date Jun 22, 2004
- STMicroelectronics, Inc.
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a field effect transistor having a channel in an e...
- Patent number 6,190,179
- Issue date Feb 20, 2001
- STMicroelectronics, Inc.
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS with parasitic bipolar transistor
- Patent number 5,723,988
- Issue date Mar 3, 1998
- Texas Instruments Incorporated
- Shivaling S. Mahant-Shetti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SRAM cell fabrication with interlevel dielectric planarization
- Patent number 5,710,461
- Issue date Jan 20, 1998
- SGS-Thomson Microelectronics, Inc.
- Loi Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a one-sided polysilicon thin film transistor
- Patent number 5,554,548
- Issue date Sep 10, 1996
- SGS-Thomson Microelectronics, Inc.
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell fabrication with interlevel dielectric planarization
- Patent number 5,395,785
- Issue date Mar 7, 1995
- SGS-Thomson Microelectronics, Inc.
- Loi Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall doping technique for SOI transistors
- Patent number 5,346,839
- Issue date Sep 13, 1994
- Texas Instruments Incorporated
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked CMOS latch with cross-coupled capacitors
- Patent number 5,347,152
- Issue date Sep 13, 1994
- Texas Instruments Incorporated
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a gate overlap LDD structure
- Patent number 5,304,504
- Issue date Apr 19, 1994
- SGS-Thomson Microelectronics, Inc.
- Che-Chia Wei
- B01 - PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
Information Patent Grant
Stacked CMOS SRAM cell with polysilicon transistor load
- Patent number 5,298,782
- Issue date Mar 29, 1994
- SGS-Thomson Microelectronics, Inc.
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI BICMOS process
- Patent number 5,294,823
- Issue date Mar 15, 1994
- Texas Instruments Incorporated
- Robert H. Eklund
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall doping technique for SOI transistors
- Patent number 5,292,670
- Issue date Mar 8, 1994
- Texas Instruments Incorporated
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Elevated CMOS
- Patent number 5,293,053
- Issue date Mar 8, 1994
- Texas Instruments Incorporated
- Satwinder S. Malhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate overlapping LDD structure
- Patent number 5,276,347
- Issue date Jan 4, 1994
- SGS-Thomson Microelectronics, Inc.
- Che-Chia Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI BICMOS process
- Patent number 5,102,809
- Issue date Apr 7, 1992
- Texas Instruments Incorporated
- Robert H. Eklund
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Elevated CMOS
- Patent number 5,072,276
- Issue date Dec 10, 1991
- Texas Instruments Incorporated
- Satwinder S. Malhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked CMOS sRAM with vertical transistors and cross-coupled capac...
- Patent number 5,016,070
- Issue date May 14, 1991
- Texas Instruments Incorporated
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin oxide sidewall insulators for silicon-over-insulator transistors
- Patent number 4,956,307
- Issue date Sep 11, 1990
- Texas Instruments, Incorporated
- Gordon P. Pollack
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Masking scheme for silicon dioxide mesa formation
- Patent number 4,950,618
- Issue date Aug 21, 1990
- Texas Instruments, Incorporated
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating stacked CMOS transistors with a self-aligned...
- Patent number 4,656,731
- Issue date Apr 14, 1987
- Texas Instruments Incorporated
- Hon W. Lam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating stacked CMOS structures
- Patent number 4,628,589
- Issue date Dec 16, 1986
- Texas Instruments Incorporated
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method of forming asymmetrical polysilicon thin film transistor
- Publication number 20040178446
- Publication date Sep 16, 2004
- Ravishankar Sundaresan
- H01 - BASIC ELECTRIC ELEMENTS

Ravishankar Sundaresan

Person

Patents Grantslast 30 patents

Sram cell fabrication with interlevel Dielectric planarization

Method and interlevel dielectric structure for improved metal step...

Method of fabricating a one-sided polysilicon thin film transistor

Method of making a field effect transistor having a channel in an e...

CMOS with parasitic bipolar transistor

SRAM cell fabrication with interlevel dielectric planarization

Method of fabricating a one-sided polysilicon thin film transistor

SRAM cell fabrication with interlevel dielectric planarization

Sidewall doping technique for SOI transistors

Stacked CMOS latch with cross-coupled capacitors

Method of forming a gate overlap LDD structure

Stacked CMOS SRAM cell with polysilicon transistor load

SOI BICMOS process

Sidewall doping technique for SOI transistors

Elevated CMOS

Gate overlapping LDD structure

SOI BICMOS process

Elevated CMOS

Stacked CMOS sRAM with vertical transistors and cross-coupled capac...

Thin oxide sidewall insulators for silicon-over-insulator transistors

Masking scheme for silicon dioxide mesa formation

Method for fabricating stacked CMOS transistors with a self-aligned...

Method for fabricating stacked CMOS structures

Patents Applicationslast 30 patents

Method of forming asymmetrical polysilicon thin film transistor