RICARDO H. BRUCE

Person

UNION CITY, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multilevel memory bus system
- Patent number 10,877,907
- Issue date Dec 29, 2020
- BiTMICRO LLC
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-dimensional computer storage system
- Patent number 10,552,050
- Issue date Feb 4, 2020
- BiTMICRO LLC
- Marlon B. Verdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scatter-gather approach for parallel data transfer in a mass storag...
- Patent number 10,489,318
- Issue date Nov 26, 2019
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage system with configurable prefetch buffers
- Patent number 10,459,842
- Issue date Oct 29, 2019
- BiTMICRO NETWORKS, Inc.
- Rey H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus arbitration with routing and failover mechanism
- Patent number 10,430,303
- Issue date Oct 1, 2019
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus arbitration with routing and failover mechanism
- Patent number 10,423,554
- Issue date Sep 24, 2019
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel memory bus system
- Patent number 10,133,686
- Issue date Nov 20, 2018
- BiTMICRO LLC
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory transaction with reduced latency
- Patent number 10,120,586
- Issue date Nov 6, 2018
- BITMICRO, LLC
- Rey H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level message passing descriptor
- Patent number 10,013,373
- Issue date Jul 3, 2018
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scatter-gather approach for parallel data transfer in a mass storag...
- Patent number 9,971,524
- Issue date May 15, 2018
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systematic method on queuing of descriptors for multiple flash inte...
- Patent number 9,952,991
- Issue date Apr 24, 2018
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Bus arbitration with routing and failover mechanism
- Patent number 9,916,213
- Issue date Mar 13, 2018
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network of memory systems
- Patent number 9,875,205
- Issue date Jan 23, 2018
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus arbitration with routing and failover mechanism
- Patent number 9,798,688
- Issue date Oct 24, 2017
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level message passing descriptor
- Patent number 9,501,436
- Issue date Nov 22, 2016
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-profile memory controller for computing devices
- Patent number 9,135,190
- Issue date Sep 15, 2015
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced latency memory read transactions in storage devices
- Patent number 8,959,307
- Issue date Feb 17, 2015
- BiTMICRO NETWORKS, Inc.
- Rey H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel memory bus system for solid-state mass storage
- Patent number 8,788,725
- Issue date Jul 22, 2014
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel memory bus system for solid-state mass storage
- Patent number 8,447,908
- Issue date May 21, 2013
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple chip module and package stacking method for storage devices
- Patent number 8,093,103
- Issue date Jan 10, 2012
- BiTMICRO NETWORKS, Inc.
- Rey H. Bruce
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple chip module and package stacking for storage devices
- Patent number 7,826,243
- Issue date Nov 2, 2010
- BiTMICRO NETWORKS, Inc.
- Rey Bruce
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for networking devices having fibre channel node function...
- Patent number 7,729,370
- Issue date Jun 1, 2010
- BiTMICRO NETWORKS, Inc.
- Jairone A. Orcine
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hardware assisted non-volatile memory-to-input/output direct memory...
- Patent number 7,620,748
- Issue date Nov 17, 2009
- BiTMICRO NETWORKS, Inc.
- Ricardo Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network storage device having solid-state non-volatile memory
- Patent number 6,981,070
- Issue date Dec 27, 2005
- Shun Hang Luk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for data recovery
- Patent number 6,970,890
- Issue date Nov 29, 2005
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel erase operations in memory systems
- Patent number 6,529,416
- Issue date Mar 4, 2003
- BiTMICRO NETWORKS, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for controlling data in a computer system in the...
- Patent number 6,496,939
- Issue date Dec 17, 2002
- Bit Microsystems, Inc.
- Roland F. Portman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified re-map and cache-index table with dual write-counters for w...
- Patent number 6,000,006
- Issue date Dec 7, 1999
- Bit Microsystems, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transparent management at host interface of flash-memory overhead-b...
- Patent number 5,956,743
- Issue date Sep 21, 1999
- Bit Microsystems, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Expandable flash-memory mass-storage using shared buddy lines and i...
- Patent number 5,822,251
- Issue date Oct 13, 1998
- Bit Microsystems, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTILEVEL MEMORY BUS SYSTEM
- Publication number 20190087363
- Publication date Mar 21, 2019
- BITMICRO LLC
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multilevel Memory Bus System
- Publication number 20140289441
- Publication date Sep 25, 2014
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multilevel Memory Bus System For Solid-State Mass Storage
- Publication number 20130246694
- Publication date Sep 19, 2013
- BiTMICRO Networks, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTILEVEL MEMORY BUS SYSTEM FOR SOLID-STATE MASS STORAGE
- Publication number 20110161568
- Publication date Jun 30, 2011
- BiTMICRO Networks, Inc.
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE CHIP MODULE AND PACKAGE STACKING METHOD FOR STORAGE DEVICES
- Publication number 20110038127
- Publication date Feb 17, 2011
- BiTMICRO Networks, Inc.
- Rey BRUCE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multiple chip module and package stacking method for storage devices
- Publication number 20070158808
- Publication date Jul 12, 2007
- Rey Bruce
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Parallel erase operations in memory systems
- Publication number 20020141244
- Publication date Oct 3, 2002
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL ERASE OPERATIONS IN MEMORY SYSTEMS
- Publication number 20020097594
- Publication date Jul 25, 2002
- Ricardo H. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR CONTROLLING DATA IN A COMPUTER SYSTEM
- Publication number 20020049917
- Publication date Apr 25, 2002
- ROLAND F. PORTMAN
- G06 - COMPUTING CALCULATING COUNTING

RICARDO H. BRUCE

Person

Patents Grantslast 30 patents

Multilevel memory bus system

Multi-dimensional computer storage system

Scatter-gather approach for parallel data transfer in a mass storag...

Data storage system with configurable prefetch buffers

Bus arbitration with routing and failover mechanism

Bus arbitration with routing and failover mechanism

Multilevel memory bus system

Memory transaction with reduced latency

Multi-level message passing descriptor

Scatter-gather approach for parallel data transfer in a mass storag...

Systematic method on queuing of descriptors for multiple flash inte...

Bus arbitration with routing and failover mechanism

Network of memory systems

Bus arbitration with routing and failover mechanism

Multi-level message passing descriptor

Multi-profile memory controller for computing devices

Reduced latency memory read transactions in storage devices

Multilevel memory bus system for solid-state mass storage

Multilevel memory bus system for solid-state mass storage

Multiple chip module and package stacking method for storage devices

Multiple chip module and package stacking for storage devices

Apparatus for networking devices having fibre channel node function...

Hardware assisted non-volatile memory-to-input/output direct memory...

Network storage device having solid-state non-volatile memory

Method and apparatus for data recovery

Parallel erase operations in memory systems

Method and system for controlling data in a computer system in the...

Unified re-map and cache-index table with dual write-counters for w...

Transparent management at host interface of flash-memory overhead-b...

Expandable flash-memory mass-storage using shared buddy lines and i...

Patents Applicationslast 30 patents

MULTILEVEL MEMORY BUS SYSTEM

Multilevel Memory Bus System

Multilevel Memory Bus System For Solid-State Mass Storage

MULTILEVEL MEMORY BUS SYSTEM FOR SOLID-STATE MASS STORAGE

MULTIPLE CHIP MODULE AND PACKAGE STACKING METHOD FOR STORAGE DEVICES

Multiple chip module and package stacking method for storage devices

Parallel erase operations in memory systems

PARALLEL ERASE OPERATIONS IN MEMORY SYSTEMS

METHOD AND SYSTEM FOR CONTROLLING DATA IN A COMPUTER SYSTEM