Richard E. Matick

Person

Cortlandt Manor, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cache line replacement techniques allowing choice of LFU or MFU cac...
- Patent number 7,958,311
- Issue date Jun 7, 2011
- International Business Machines Corporation
- Richard Edward Matick
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Cache line replacement techniques allowing choice of LFU or MFU cac...
- Patent number 7,870,341
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Richard Edward Matick
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
eDRAM hierarchical differential sense AMP
- Patent number 7,821,858
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical 2T-DRAM with self-timed sensing
- Patent number 7,709,299
- Issue date May 4, 2010
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast, stable, SRAM cell using seven devices and hierarchical bit/se...
- Patent number 7,499,312
- Issue date Mar 3, 2009
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical six-transistor SRAM
- Patent number 7,471,546
- Issue date Dec 30, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
eDRAM hierarchical differential sense amp
- Patent number 7,460,387
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical 2T-DRAM with self-timed sensing
- Patent number 7,460,423
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache line replacement techniques allowing choice of LFU or MFU cac...
- Patent number 7,398,357
- Issue date Jul 8, 2008
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM hierarchical data path
- Patent number 7,289,369
- Issue date Oct 30, 2007
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache with selective least frequently used or most frequently used...
- Patent number 7,133,971
- Issue date Nov 7, 2006
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping and logic for combining L1 and L2 directories and/or arrays
- Patent number 6,981,096
- Issue date Dec 27, 2005
- International Business Machines Corporation
- Richard E. Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache reloading performance improvement through the use of early se...
- Patent number 6,081,872
- Issue date Jun 27, 2000
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated processing and L2 DRAM cache
- Patent number 5,895,487
- Issue date Apr 20, 1999
- International Business Machines Corporation
- William Todd Boyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic computer memory system having multiple width, high speed...
- Patent number 5,890,215
- Issue date Mar 30, 1999
- International Business Machines Corporation
- Richard E. Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information handling system including mapping of graphics display d...
- Patent number 5,870,108
- Issue date Feb 9, 1999
- International Business Machines Corporation
- Inching Chen
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Bit line switch array for electronic computer memory
- Patent number 5,388,072
- Issue date Feb 7, 1995
- International Business Machines Corporation
- Richard E. Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional cache memory chip architecture for improved cache access
- Patent number 4,905,188
- Issue date Feb 27, 1990
- International Business Machines Corporation
- Chiao-Mei Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits for accessing a variable width data bus with a variable wi...
- Patent number 4,667,305
- Issue date May 19, 1987
- International Business Machines Corporation
- Frederick H. Dill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Display architecture having variable data width
- Patent number 4,663,729
- Issue date May 5, 1987
- International Business Machines Corp.
- Richard E. Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic row buffer circuit for DRAM
- Patent number 4,649,516
- Issue date Mar 10, 1987
- International Business Machines Corp.
- Paul W. Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Communicating random access memory
- Patent number 4,616,310
- Issue date Oct 7, 1986
- International Business Machines Corporation
- Frederick H. Dill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data buffer having separate lock bit storage array
- Patent number 4,589,092
- Issue date May 13, 1986
- International Business Machines Corporation
- Richard E. Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed, on-chip cache
- Patent number 4,577,293
- Issue date Mar 18, 1986
- International Business Machines Corporation
- Richard E. Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Random access memory having a second input/output port
- Patent number 4,541,075
- Issue date Sep 10, 1985
- International Business Machines Corporation
- Frederick H. Dill
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
High speed high density, multi-port random access memory cell
- Patent number 4,287,575
- Issue date Sep 1, 1981
- International Business Machines Corporation
- David B. Eardley
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid semiconductor memory with on-chip associative page addressin...
- Patent number 4,084,230
- Issue date Apr 11, 1978
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CAC...
- Publication number 20090182951
- Publication date Jul 16, 2009
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
eDRAM Hierarchical Differential Sense AMP
- Publication number 20090080230
- Publication date Mar 26, 2009
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CAC...
- Publication number 20090031084
- Publication date Jan 29, 2009
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING
- Publication number 20080308941
- Publication date Dec 18, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR A DRAM CONCURRENT REFRESH ENGINE WITH PROCE...
- Publication number 20080270683
- Publication date Oct 30, 2008
- International Business Machines Corporation
- John E. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP
- Publication number 20080165601
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
Hierarchical 2T-DRAM with Self-Timed Sensing
- Publication number 20080165560
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
FAST, STABLE, SRAM CELL USING SEVEN DEVICES AND HIERARCHICAL BIT/SE...
- Publication number 20080165562
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
HIERARCHICAL SIX-TRANSISTOR SRAM
- Publication number 20080165561
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CAC...
- Publication number 20080147982
- Publication date Jun 19, 2008
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM HIERARCHICAL DATA PATH
- Publication number 20080016277
- Publication date Jan 17, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM hierarchical data path
- Publication number 20060233024
- Publication date Oct 19, 2006
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
Cache with selective least frequently used or most frequently used...
- Publication number 20050114606
- Publication date May 26, 2005
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING

Richard E. Matick

Person

Patents Grantslast 30 patents

Cache line replacement techniques allowing choice of LFU or MFU cac...

Cache line replacement techniques allowing choice of LFU or MFU cac...

eDRAM hierarchical differential sense AMP

Hierarchical 2T-DRAM with self-timed sensing

Fast, stable, SRAM cell using seven devices and hierarchical bit/se...

Hierarchical six-transistor SRAM

eDRAM hierarchical differential sense amp

Hierarchical 2T-DRAM with self-timed sensing

Cache line replacement techniques allowing choice of LFU or MFU cac...

DRAM hierarchical data path

Cache with selective least frequently used or most frequently used...

Mapping and logic for combining L1 and L2 directories and/or arrays

Cache reloading performance improvement through the use of early se...

Integrated processing and L2 DRAM cache

Electronic computer memory system having multiple width, high speed...

Information handling system including mapping of graphics display d...

Bit line switch array for electronic computer memory

Functional cache memory chip architecture for improved cache access

Circuits for accessing a variable width data bus with a variable wi...

Display architecture having variable data width

Dynamic row buffer circuit for DRAM

Communicating random access memory

Data buffer having separate lock bit storage array

Distributed, on-chip cache

Random access memory having a second input/output port

High speed high density, multi-port random access memory cell

Hybrid semiconductor memory with on-chip associative page addressin...

Patents Applicationslast 30 patents

CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CAC...

eDRAM Hierarchical Differential Sense AMP

CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CAC...

HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING

SYSTEMS AND METHODS FOR A DRAM CONCURRENT REFRESH ENGINE WITH PROCE...

eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP

Hierarchical 2T-DRAM with Self-Timed Sensing

FAST, STABLE, SRAM CELL USING SEVEN DEVICES AND HIERARCHICAL BIT/SE...

HIERARCHICAL SIX-TRANSISTOR SRAM

CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CAC...

DRAM HIERARCHICAL DATA PATH

DRAM hierarchical data path

Cache with selective least frequently used or most frequently used...