Richard Ferrant

Person

St Ismier, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Look-up table architecture
- Patent number 10,110,235
- Issue date Oct 23, 2018
- Soitec
- Richard Ferrant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Look-up table
- Patent number 9,621,168
- Issue date Apr 11, 2017
- Soitec
- Richard Ferrant
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory device with dynamically operated reference circuits
- Patent number 9,576,642
- Issue date Feb 21, 2017
- Soitec
- Roland Thewes
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-inverter circuit with multiple independent gate transistors
- Patent number 9,496,877
- Issue date Nov 15, 2016
- Soitec
- Carlos Mazure
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device having a contact between semiconductor regions through a bur...
- Patent number 9,490,264
- Issue date Nov 8, 2016
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tristate gate
- Patent number 9,479,174
- Issue date Oct 25, 2016
- Soitec
- Richard Ferrant
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit and method for sensing a difference in voltage on a pair of...
- Patent number 9,390,771
- Issue date Jul 12, 2016
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with dual gate precharge and decode transistors
- Patent number 9,251,871
- Issue date Feb 2, 2016
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Eprom cell
- Patent number 9,230,662
- Issue date Jan 5, 2016
- Soitec
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump circuit comprising multiple—gate transistors and method...
- Patent number 9,225,237
- Issue date Dec 29, 2015
- Soitec
- Richard Ferrant
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Semiconductor memory having staggered sense amplifiers associated w...
- Patent number 9,159,400
- Issue date Oct 13, 2015
- Soitec
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential sense amplifier without switch transistors
- Patent number 9,135,964
- Issue date Sep 15, 2015
- Soitec
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential sense amplifier without dedicated precharge transistors
- Patent number 9,111,593
- Issue date Aug 18, 2015
- Soitec
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for manufacturing a semiconductor substrate
- Patent number 9,035,474
- Issue date May 19, 2015
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential sense amplifier without dedicated pass-gate transistors
- Patent number 8,953,399
- Issue date Feb 10, 2015
- Soitech
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory cell on SeOI having a second control gate buried under...
- Patent number 8,664,712
- Issue date Mar 4, 2014
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pseudo-inverter circuit on SeOI
- Patent number 8,654,602
- Issue date Feb 18, 2014
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-layer structures and process for fabricating semiconductor de...
- Patent number 8,652,887
- Issue date Feb 18, 2014
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano-sense amplifier
- Patent number 8,625,374
- Issue date Jan 7, 2014
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM-type memory cell
- Patent number 8,575,697
- Issue date Nov 5, 2013
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Data-path cell on an SeOI substrate with a back control gate beneat...
- Patent number 8,508,289
- Issue date Aug 13, 2013
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device comprising a field-effect transistor in a silicon-on-insulator
- Patent number 8,455,938
- Issue date Jun 4, 2013
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data-path cell on an SeOI substrate with a back control gate beneat...
- Patent number 8,432,216
- Issue date Apr 30, 2013
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrays of transistors with back control gates buried beneath the in...
- Patent number 8,384,425
- Issue date Feb 26, 2013
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano-sense amplifier
- Patent number 8,358,552
- Issue date Jan 22, 2013
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices and methods for comparing data in a content-addressable memory
- Patent number 8,325,506
- Issue date Dec 4, 2012
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM device structure employing thermally-assisted write operations...
- Patent number 8,310,866
- Issue date Nov 13, 2012
- Qimonda AG
- Rainer Leuschner
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Memory cell with a channel buried beneath a dielectric layer
- Patent number 8,304,833
- Issue date Nov 6, 2012
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM memory cell having a vertical bipolar injector
- Patent number 8,305,803
- Issue date Nov 6, 2012
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Bus with error correction circuitry
- Patent number 8,266,494
- Issue date Sep 11, 2012
- STMicroelectronics (Crolles 2) SAS
- Richard Ferrant
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE WITH DYNAMICALLY OPERATED REFERENCE CIRCUITS
- Publication number 20160086652
- Publication date Mar 24, 2016
- SOITEC
- Roland Thewes
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE PUMP CIRCUIT COMPRISING MULTIPLE - GATE TRANSISTORS AND METH...
- Publication number 20150263610
- Publication date Sep 17, 2015
- SOITEC
- Richard Ferrant
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
COMPLEMENTARY FET INJECTION FOR A FLOATING BODY CELL
- Publication number 20150145049
- Publication date May 28, 2015
- SOITEC
- Franz Hoffman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPROM CELL
- Publication number 20150042381
- Publication date Feb 12, 2015
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
LOOK-UP TABLE ARCHITECTURE
- Publication number 20150035562
- Publication date Feb 5, 2015
- SOITEC
- Richard Ferrant
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLEXER, LOOK-UP TABLE AND FPGA
- Publication number 20150028920
- Publication date Jan 29, 2015
- SOITEC
- Richard Ferrant
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOOK-UP TABLE
- Publication number 20150022237
- Publication date Jan 22, 2015
- SOITEC
- Richard Ferrant
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUIT AND METHOD FOR SENSING A DIFFERENCE IN VOLTAGE ON A PAIR OF...
- Publication number 20140376318
- Publication date Dec 25, 2014
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
TRISTATE GATE
- Publication number 20140340118
- Publication date Nov 20, 2014
- Richard Ferrant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SENSE AMPLIFIER WITH DUAL GATE PRECHARGE AND DECODE TRANSISTORS
- Publication number 20140321225
- Publication date Oct 30, 2014
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS
- Publication number 20140225648
- Publication date Aug 14, 2014
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
NANO-SENSE AMPLIFIER
- Publication number 20130100749
- Publication date Apr 25, 2013
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
DIFFERENTIAL SENSE AMPLIFIER WITHOUT SWITCH TRANSISTORS
- Publication number 20120275252
- Publication date Nov 1, 2012
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PASS-GATE TRANSISTORS
- Publication number 20120275253
- Publication date Nov 1, 2012
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PRECHARGE TRANSISTORS
- Publication number 20120275254
- Publication date Nov 1, 2012
- SOITEC
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-INVERTER CIRCUIT ON SeOI
- Publication number 20120250444
- Publication date Oct 4, 2012
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED W...
- Publication number 20120243360
- Publication date Sep 27, 2012
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DE...
- Publication number 20120231606
- Publication date Sep 13, 2012
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR
- Publication number 20110260233
- Publication date Oct 27, 2011
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE
- Publication number 20110241157
- Publication date Oct 6, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-INVERTER CIRCUIT ON SeO1
- Publication number 20110242926
- Publication date Oct 6, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM-TYPE MEMORY CELL
- Publication number 20110233675
- Publication date Sep 29, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
NANO-SENSE AMPLIFIER
- Publication number 20110222361
- Publication date Sep 15, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEAT...
- Publication number 20110215860
- Publication date Sep 8, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL WITH A CHANNEL BURIED BENEATH A DIELECTRIC LAYER
- Publication number 20110169087
- Publication date Jul 14, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR
- Publication number 20110170343
- Publication date Jul 14, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY
- Publication number 20110170327
- Publication date Jul 14, 2011
- Carlos Mazure
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DEVICE HAVING A CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH A BUR...
- Publication number 20110169090
- Publication date Jul 14, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEAT...
- Publication number 20110133822
- Publication date Jun 9, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER...
- Publication number 20110134698
- Publication date Jun 9, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS

Richard Ferrant

Person

Patents Grantslast 30 patents

Look-up table architecture

Look-up table

Memory device with dynamically operated reference circuits

Pseudo-inverter circuit with multiple independent gate transistors

Device having a contact between semiconductor regions through a bur...

Tristate gate

Circuit and method for sensing a difference in voltage on a pair of...

Sense amplifier with dual gate precharge and decode transistors

Eprom cell

Charge pump circuit comprising multiple—gate transistors and method...

Semiconductor memory having staggered sense amplifiers associated w...

Differential sense amplifier without switch transistors

Differential sense amplifier without dedicated precharge transistors

Method for manufacturing a semiconductor substrate

Differential sense amplifier without dedicated pass-gate transistors

Flash memory cell on SeOI having a second control gate buried under...

Pseudo-inverter circuit on SeOI

Multi-layer structures and process for fabricating semiconductor de...

Nano-sense amplifier

SRAM-type memory cell

Data-path cell on an SeOI substrate with a back control gate beneat...

Device comprising a field-effect transistor in a silicon-on-insulator

Data-path cell on an SeOI substrate with a back control gate beneat...

Arrays of transistors with back control gates buried beneath the in...

Nano-sense amplifier

Devices and methods for comparing data in a content-addressable memory

MRAM device structure employing thermally-assisted write operations...

Memory cell with a channel buried beneath a dielectric layer

DRAM memory cell having a vertical bipolar injector

Bus with error correction circuitry

Patents Applicationslast 30 patents

MEMORY DEVICE WITH DYNAMICALLY OPERATED REFERENCE CIRCUITS

CHARGE PUMP CIRCUIT COMPRISING MULTIPLE - GATE TRANSISTORS AND METH...

COMPLEMENTARY FET INJECTION FOR A FLOATING BODY CELL

EPROM CELL

LOOK-UP TABLE ARCHITECTURE

MULTIPLEXER, LOOK-UP TABLE AND FPGA

LOOK-UP TABLE

CIRCUIT AND METHOD FOR SENSING A DIFFERENCE IN VOLTAGE ON A PAIR OF...

TRISTATE GATE

SENSE AMPLIFIER WITH DUAL GATE PRECHARGE AND DECODE TRANSISTORS

PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS

NANO-SENSE AMPLIFIER

DIFFERENTIAL SENSE AMPLIFIER WITHOUT SWITCH TRANSISTORS

DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PASS-GATE TRANSISTORS

DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PRECHARGE TRANSISTORS

PSEUDO-INVERTER CIRCUIT ON SeOI

SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED W...

MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DE...

DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR

METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE

PSEUDO-INVERTER CIRCUIT ON SeO1

SRAM-TYPE MEMORY CELL

NANO-SENSE AMPLIFIER

DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEAT...

MEMORY CELL WITH A CHANNEL BURIED BENEATH A DIELECTRIC LAYER

DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR

DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY

DEVICE HAVING A CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH A BUR...

DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEAT...

FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER...