Richard J. McPartland

Person

Nazareth, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Secure random number generator
- Patent number 8,566,377
- Issue date Oct 22, 2013
- Agere Systems LLC
- Edward B. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimization of circuits having repeatable circuit instances
- Patent number 8,516,408
- Issue date Aug 20, 2013
- LSI Corporation
- Richard Bruce Dell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-reliability memory
- Patent number 8,468,419
- Issue date Jun 18, 2013
- LSI Corporation
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit self-monitored burn-in
- Patent number 8,405,412
- Issue date Mar 26, 2013
- LSI Corporation
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with phase distribution circuit for controlling relat...
- Patent number 8,284,622
- Issue date Oct 9, 2012
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory built-in self-characterization
- Patent number 8,169,844
- Issue date May 1, 2012
- Agere Systems Inc.
- Kouros Azimi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with error correction capability and efficient partia...
- Patent number 8,156,402
- Issue date Apr 10, 2012
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Systematic error correction for multi-level flash memory
- Patent number 8,139,412
- Issue date Mar 20, 2012
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing a memory device
- Patent number 8,023,348
- Issue date Sep 20, 2011
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a memory with process-voltage-temperature...
- Patent number 7,948,819
- Issue date May 24, 2011
- Agere Systems Inc.
- Mathew R. Henry
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for increasing yield in a memory device
- Patent number 7,940,594
- Issue date May 10, 2011
- Agere Systems Inc.
- Richard Bruce Dell
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with error correction capability and preemptive parti...
- Patent number 7,930,615
- Issue date Apr 19, 2011
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Accessing memory cells in a memory circuit
- Patent number 7,872,929
- Issue date Jan 18, 2011
- LSI Corporation
- Richard Bruce Dell
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for hot carrier programmed one time programmab...
- Patent number 7,764,541
- Issue date Jul 27, 2010
- Agere Systems Inc.
- Ross Alan Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple-level memory with analog read
- Patent number 7,746,692
- Issue date Jun 29, 2010
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory with low-power refresh
- Patent number 7,742,355
- Issue date Jun 22, 2010
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced leakage driver circuit and memory device employing same
- Patent number 7,633,830
- Issue date Dec 15, 2009
- Agere Systems Inc.
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for idle cycle refresh request in DRAM
- Patent number 7,613,061
- Issue date Nov 3, 2009
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-port memory
- Patent number 7,551,512
- Issue date Jun 23, 2009
- Agere Systems Inc.
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing leakage current in a read only me...
- Patent number 7,460,424
- Issue date Dec 2, 2008
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory repair methodology using quasi-non-volatile me...
- Patent number 7,295,480
- Issue date Nov 13, 2007
- Agere Systems Inc.
- Richard J. McPartland
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self test for memory arrays using error correction coding
- Patent number 7,254,763
- Issue date Aug 7, 2007
- Agere Systems Inc.
- Duane Rodney Aadsen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing leakage current in a read only me...
- Patent number 7,177,212
- Issue date Feb 13, 2007
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing leakage current in a read only me...
- Patent number 7,085,149
- Issue date Aug 1, 2006
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing leakage current in a read only me...
- Patent number 7,042,779
- Issue date May 9, 2006
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for programming a one-time programmable memory...
- Patent number 7,002,829
- Issue date Feb 21, 2006
- Agere Systems Inc.
- Ranbir Singh
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-only memory architecture
- Patent number 6,879,509
- Issue date Apr 12, 2005
- Agere Systems, INC
- Donald A. Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage flash EEPROM memory cell with improved data retention
- Patent number 6,661,705
- Issue date Dec 9, 2003
- Agere Systems Inc.
- Richard J. McPartland
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage flash EEPROM memory cell with improved data retention
- Patent number 6,552,931
- Issue date Apr 22, 2003
- Agere Systems Inc.
- Richard J. McPartland
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile semiconductor memory cell utilizing trapped charge gen...
- Patent number 6,528,845
- Issue date Mar 4, 2003
- Lucent Technologies Inc.
- Jeffrey D. Bude
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Memory Device with Phase Distribution Circuit for Controlling Relat...
- Publication number 20120075946
- Publication date Mar 29, 2012
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Cell Using Leakage Current Storage Mechanism
- Publication number 20110157964
- Publication date Jun 30, 2011
- Richard J. McPartland
- G11 - INFORMATION STORAGE
Information Patent Application
High-Reliability Memory
- Publication number 20110055660
- Publication date Mar 3, 2011
- Dennis E. Dudeck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure Random Number Generator
- Publication number 20110022648
- Publication date Jan 27, 2011
- Edward B. Harris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Built-In Self-Characterization
- Publication number 20100329054
- Publication date Dec 30, 2010
- Kouros Azimi
- G11 - INFORMATION STORAGE
Information Patent Application
Optimization of Circuits Having Repeatable Circuit Instances
- Publication number 20100301926
- Publication date Dec 2, 2010
- Richard Bruce Dell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Self-Monitored Burn-In
- Publication number 20100271064
- Publication date Oct 28, 2010
- Ross A. Kohler
- G01 - MEASURING TESTING
Information Patent Application
Accessing Memory Cells in a Memory Circuit
- Publication number 20100271891
- Publication date Oct 28, 2010
- Richard Bruce Dell
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Increasing Yield in a Memory Device
- Publication number 20100238751
- Publication date Sep 23, 2010
- Agere Systems Inc.
- Richard Bruce Dell
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY
- Publication number 20100229035
- Publication date Sep 9, 2010
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Testing a Memory Device
- Publication number 20100182859
- Publication date Jul 22, 2010
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device with Error Correction Capability and Efficient Partia...
- Publication number 20100131825
- Publication date May 27, 2010
- Ross A. Kohler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple-Level Memory with Analog Read
- Publication number 20090196098
- Publication date Aug 6, 2009
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic Random Access Memory With Low-Power Refresh
- Publication number 20090161459
- Publication date Jun 25, 2009
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Reduced Leakage Driver Circuit and Memory Device Employing Same
- Publication number 20090141580
- Publication date Jun 4, 2009
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Idle Cycle Refresh Request in Dram
- Publication number 20090141575
- Publication date Jun 4, 2009
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Dual-Port Memory
- Publication number 20090034356
- Publication date Feb 5, 2009
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device with Error Correction Capability and Preemptive Parti...
- Publication number 20080301526
- Publication date Dec 4, 2008
- Ross A. Kohler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT HAVING A MEMORY WITH PROCESS-VOLTAGE-TEMPERATURE...
- Publication number 20080117702
- Publication date May 22, 2008
- Agere Systems Inc.
- Matthew R. Henry
- G11 - INFORMATION STORAGE
Information Patent Application
Method And Apparatus For Hot Carrier Programmed One Time Programmab...
- Publication number 20070274126
- Publication date Nov 29, 2007
- Ross Alan Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Method And Apparatus For Reducing Leakage Current In A Read Only Me...
- Publication number 20070103959
- Publication date May 10, 2007
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Built-in self test for memory arrays using error correction coding
- Publication number 20060048031
- Publication date Mar 2, 2006
- Agere Systems, Inc.
- Duane Rodney Aadsen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing leakage current in a read only me...
- Publication number 20050162951
- Publication date Jul 28, 2005
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reducing leakage current in a read only me...
- Publication number 20050162941
- Publication date Jul 28, 2005
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reducing leakage current in a read only me...
- Publication number 20050162952
- Publication date Jul 28, 2005
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory repair methodology using quasi-non-volatile me...
- Publication number 20050149782
- Publication date Jul 7, 2005
- Richard J. McPartland
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and method for programming a one-time programmable memory...
- Publication number 20050070052
- Publication date Mar 31, 2005
- Ranbir Singh
- G11 - INFORMATION STORAGE
Information Patent Application
Read-only memory architecture
- Publication number 20040233693
- Publication date Nov 25, 2004
- Agere Systems, Inc.
- Donald A. Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Low voltage flash EEPROM memory cell with improved data retention
- Publication number 20020015327
- Publication date Feb 7, 2002
- Agere Systems Guardian Corp.
- Richard J. McPartland
- H01 - BASIC ELECTRIC ELEMENTS

Richard J. McPartland

Person

Patents Grantslast 30 patents

Secure random number generator

Optimization of circuits having repeatable circuit instances

High-reliability memory

Integrated circuit self-monitored burn-in

Memory device with phase distribution circuit for controlling relat...

Memory built-in self-characterization

Memory device with error correction capability and efficient partia...

Systematic error correction for multi-level flash memory

Method and apparatus for testing a memory device

Integrated circuit having a memory with process-voltage-temperature...

Method and apparatus for increasing yield in a memory device

Memory device with error correction capability and preemptive parti...

Accessing memory cells in a memory circuit

Method and apparatus for hot carrier programmed one time programmab...

Multiple-level memory with analog read

Dynamic random access memory with low-power refresh

Reduced leakage driver circuit and memory device employing same

Method and apparatus for idle cycle refresh request in DRAM

Dual-port memory

Method and apparatus for reducing leakage current in a read only me...

Semiconductor memory repair methodology using quasi-non-volatile me...

Built-in self test for memory arrays using error correction coding

Method and apparatus for reducing leakage current in a read only me...

Method and apparatus for reducing leakage current in a read only me...

Method and apparatus for reducing leakage current in a read only me...

Apparatus and method for programming a one-time programmable memory...

Read-only memory architecture

Low voltage flash EEPROM memory cell with improved data retention

Low voltage flash EEPROM memory cell with improved data retention

Non-volatile semiconductor memory cell utilizing trapped charge gen...

Patents Applicationslast 30 patents

Memory Device with Phase Distribution Circuit for Controlling Relat...

Memory Cell Using Leakage Current Storage Mechanism

High-Reliability Memory

Secure Random Number Generator

Memory Built-In Self-Characterization

Optimization of Circuits Having Repeatable Circuit Instances

Integrated Circuit Self-Monitored Burn-In

Accessing Memory Cells in a Memory Circuit

Method and Apparatus for Increasing Yield in a Memory Device

SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY

Method and Apparatus for Testing a Memory Device

Memory Device with Error Correction Capability and Efficient Partia...

Multiple-Level Memory with Analog Read

Dynamic Random Access Memory With Low-Power Refresh

Reduced Leakage Driver Circuit and Memory Device Employing Same

Method and Apparatus for Idle Cycle Refresh Request in Dram

Dual-Port Memory

Memory Device with Error Correction Capability and Preemptive Parti...

INTEGRATED CIRCUIT HAVING A MEMORY WITH PROCESS-VOLTAGE-TEMPERATURE...

Method And Apparatus For Hot Carrier Programmed One Time Programmab...

Method And Apparatus For Reducing Leakage Current In A Read Only Me...

Built-in self test for memory arrays using error correction coding

Method and apparatus for reducing leakage current in a read only me...

Method and apparatus for reducing leakage current in a read only me...

Method and apparatus for reducing leakage current in a read only me...

Semiconductor memory repair methodology using quasi-non-volatile me...

Apparatus and method for programming a one-time programmable memory...

Read-only memory architecture

Low voltage flash EEPROM memory cell with improved data retention