Richard M. Barth

Person

Ashland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Controlling DRAM at time DRAM ready to receive command when exiting...
- Patent number 8,756,395
- Issue date Jun 17, 2014
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for indicating mask information
- Patent number 8,560,797
- Issue date Oct 15, 2013
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip having register to store value that represents adjustment to r...
- Patent number 8,458,385
- Issue date Jun 4, 2013
- Rambus Inc.
- Mark A. Horowitz
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having multiple power modes
- Patent number 8,305,839
- Issue date Nov 6, 2012
- Rambus Inc.
- Ely K. Tsern
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for adjusting the performance of a synchronous...
- Patent number 8,296,540
- Issue date Oct 23, 2012
- Rambus Inc.
- Bruno Werner Garlepp
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of controlling a memory device having multiple power modes
- Patent number 8,248,884
- Issue date Aug 21, 2012
- Rambus Inc.
- Ely K. Tsern
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller and method utilizing equalization co-efficient se...
- Patent number 8,214,570
- Issue date Jul 3, 2012
- Rambus Inc.
- Mark A. Horowitz
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller for controlling write signaling
- Patent number 8,205,056
- Issue date Jun 19, 2012
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of operation of a memory device and system including initial...
- Patent number 8,127,152
- Issue date Feb 28, 2012
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory write signaling and methods thereof
- Patent number 8,019,958
- Issue date Sep 13, 2011
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
System and dynamic random access memory device having a receiver
- Patent number 8,001,305
- Issue date Aug 16, 2011
- Rambus Inc.
- Mark A. Horowitz
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having multiple power modes
- Patent number 7,986,584
- Issue date Jul 26, 2011
- Rambus Inc.
- Ely K. Tsern
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface for a semiconductor memory device and method for controll...
- Patent number 7,793,039
- Issue date Sep 7, 2010
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having a read pipeline and a delay locked loop
- Patent number 7,626,880
- Issue date Dec 1, 2009
- Rambus Inc.
- Ely K. Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for a memory device having a power down mode and method
- Patent number 7,581,121
- Issue date Aug 25, 2009
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having a power down exit register
- Patent number 7,574,616
- Issue date Aug 11, 2009
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and module including a memory device having a power down mode
- Patent number 7,571,330
- Issue date Aug 4, 2009
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit memory device and signaling method for adjusting...
- Patent number 7,565,468
- Issue date Jul 21, 2009
- Rambus Inc.
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device and signaling method with topographic dep...
- Patent number 7,546,390
- Issue date Jun 9, 2009
- Rambus, Inc.
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device and signaling method with phase control b...
- Patent number 7,539,802
- Issue date May 26, 2009
- Rambus Inc.
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Expandable slave device system with buffered subsystems
- Patent number 7,536,494
- Issue date May 19, 2009
- Rambus Inc.
- Bruno W. Garlepp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit memory device having delayed write timing based...
- Patent number 7,496,709
- Issue date Feb 24, 2009
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory device having delayed write capability
- Patent number 7,360,050
- Issue date Apr 15, 2008
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for pipelined memory operations
- Patent number 7,353,357
- Issue date Apr 1, 2008
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory Device Having a Configurable Oscillator for Refresh Operation
- Patent number 7,349,279
- Issue date Mar 25, 2008
- Rambus Inc.
- Ely K. Tsern
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for adjusting the performance of a synchronous...
- Patent number 7,337,294
- Issue date Feb 26, 2008
- Rambus Inc.
- Bruno Werner Garlepp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system having delayed write timing
- Patent number 7,330,953
- Issue date Feb 12, 2008
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory device having delayed write timing based...
- Patent number 7,330,952
- Issue date Feb 12, 2008
- Rambus Inc.
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for pipelined memory operations
- Patent number 7,330,951
- Issue date Feb 12, 2008
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power control system for synchronous memory device
- Patent number 7,320,082
- Issue date Jan 15, 2008
- Rambus Inc.
- Ely K. Tsern
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Chip Having Register to Store Value that Represents Adjustment to R...
- Publication number 20130227214
- Publication date Aug 29, 2013
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip Having Register to Store Value that Represents Adjustment to R...
- Publication number 20120268199
- Publication date Oct 25, 2012
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF OPERATION OF A MEMORY DEVICE AND SYSTEM INCLUDING INITIAL...
- Publication number 20120216059
- Publication date Aug 23, 2012
- RAMBUS INC.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE COMPRISES AN INTERFACE TO TRANSMIT A FIRS...
- Publication number 20120201089
- Publication date Aug 9, 2012
- RAMBUS INC.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Indicating Mask Information
- Publication number 20120173810
- Publication date Jul 5, 2012
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Delaying Write Operations
- Publication number 20120173811
- Publication date Jul 5, 2012
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device Having Multiple Power Modes
- Publication number 20120113738
- Publication date May 10, 2012
- Ely K. Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Device Having Multiple Power Modes
- Publication number 20120057424
- Publication date Mar 8, 2012
- Ely K. Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Controller for Controlling Write Signaling
- Publication number 20120005437
- Publication date Jan 5, 2012
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Controller and Method Utilizing Equalization Co-Efficient Se...
- Publication number 20110289245
- Publication date Nov 24, 2011
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Device Having Multiple Power Modes
- Publication number 20110090755
- Publication date Apr 21, 2011
- Ely K. Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Write Signaling and Methods Thereof
- Publication number 20100332719
- Publication date Dec 30, 2010
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device Having a Read Pipeline and a Delay Locked Loop
- Publication number 20100046314
- Publication date Feb 25, 2010
- Ely K. Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Dynamic Random Access Memory Device Having a Receiver
- Publication number 20090248971
- Publication date Oct 1, 2009
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Memory Device Having Delayed Write Timing Based...
- Publication number 20090129178
- Publication date May 21, 2009
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR ADJUSTING THE PERFORMANCE OF A SYNCHRONOUS...
- Publication number 20080162759
- Publication date Jul 3, 2008
- RAMBUS INC.
- Bruno Werner Garlepp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit memory device having delayed write timing based...
- Publication number 20080091907
- Publication date Apr 17, 2008
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Device and Signaling Method with Phase Control B...
- Publication number 20080071951
- Publication date Mar 20, 2008
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Device and Signaling Method with Topographic Dep...
- Publication number 20080052434
- Publication date Feb 28, 2008
- RAMBUS INC.
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Memory Device and Signaling Method with Topograp...
- Publication number 20080052440
- Publication date Feb 28, 2008
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Controlling A Memory Device Having a Memory Core
- Publication number 20080043546
- Publication date Feb 21, 2008
- RAMBUS INC.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Device Having a Delay Locked Loop and Multiple Power Modes
- Publication number 20080002516
- Publication date Jan 3, 2008
- Ely K. Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Memory Device Having Delayed Write Timing Based...
- Publication number 20070242532
- Publication date Oct 18, 2007
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Device that Stores a Value Representative of an...
- Publication number 20070239914
- Publication date Oct 11, 2007
- Mark A. Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Expandable Slave Device System with Buffered Subsystems
- Publication number 20070220188
- Publication date Sep 20, 2007
- Bruno W. Garlepp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE
- Publication number 20070201280
- Publication date Aug 30, 2007
- RAMBUS INC.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory System Having Delayed Write Timing
- Publication number 20070198868
- Publication date Aug 23, 2007
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Memory Device with Delayed Write Command Processing
- Publication number 20070159912
- Publication date Jul 12, 2007
- Richard M. Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device Having a Configurable Oscillator for Refresh Operation
- Publication number 20070147155
- Publication date Jun 28, 2007
- Ely K. Tsern
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Memory Device Having Delayed Write Capability
- Publication number 20070147143
- Publication date Jun 28, 2007
- Richard M. Barth
- G11 - INFORMATION STORAGE

Richard M. Barth

Person

Patents Grantslast 30 patents

Controlling DRAM at time DRAM ready to receive command when exiting...

Method and apparatus for indicating mask information

Chip having register to store value that represents adjustment to r...

Memory device having multiple power modes

Method and apparatus for adjusting the performance of a synchronous...

Method of controlling a memory device having multiple power modes

Memory controller and method utilizing equalization co-efficient se...

Memory controller for controlling write signaling

Method of operation of a memory device and system including initial...

Memory write signaling and methods thereof

System and dynamic random access memory device having a receiver

Memory device having multiple power modes

Interface for a semiconductor memory device and method for controll...

Memory device having a read pipeline and a delay locked loop

System for a memory device having a power down mode and method

Memory device having a power down exit register

System and module including a memory device having a power down mode

Integrated circuit memory device and signaling method for adjusting...

Integrated circuit device and signaling method with topographic dep...

Integrated circuit device and signaling method with phase control b...

Expandable slave device system with buffered subsystems

Integrated circuit memory device having delayed write timing based...

Integrated circuit memory device having delayed write capability

Apparatus and method for pipelined memory operations

Memory Device Having a Configurable Oscillator for Refresh Operation

Method and apparatus for adjusting the performance of a synchronous...

Memory system having delayed write timing

Integrated circuit memory device having delayed write timing based...

Apparatus and method for pipelined memory operations

Power control system for synchronous memory device

Patents Applicationslast 30 patents

Chip Having Register to Store Value that Represents Adjustment to R...

Chip Having Register to Store Value that Represents Adjustment to R...

METHOD OF OPERATION OF A MEMORY DEVICE AND SYSTEM INCLUDING INITIAL...

INTEGRATED CIRCUIT DEVICE COMPRISES AN INTERFACE TO TRANSMIT A FIRS...

Method and Apparatus for Indicating Mask Information

Method and Apparatus for Delaying Write Operations

Memory Device Having Multiple Power Modes

Memory Device Having Multiple Power Modes

Memory Controller for Controlling Write Signaling

Memory Controller and Method Utilizing Equalization Co-Efficient Se...

Memory Device Having Multiple Power Modes

Memory Write Signaling and Methods Thereof

Memory Device Having a Read Pipeline and a Delay Locked Loop

System and Dynamic Random Access Memory Device Having a Receiver

Integrated Circuit Memory Device Having Delayed Write Timing Based...

METHOD AND APPARATUS FOR ADJUSTING THE PERFORMANCE OF A SYNCHRONOUS...

Integrated circuit memory device having delayed write timing based...

Integrated Circuit Device and Signaling Method with Phase Control B...

Integrated Circuit Device and Signaling Method with Topographic Dep...

Integrated Circuit Memory Device and Signaling Method with Topograp...

Method of Controlling A Memory Device Having a Memory Core

Memory Device Having a Delay Locked Loop and Multiple Power Modes

Integrated Circuit Memory Device Having Delayed Write Timing Based...

Integrated Circuit Device that Stores a Value Representative of an...

Expandable Slave Device System with Buffered Subsystems

MEMORY DEVICE

Memory System Having Delayed Write Timing

Integrated Circuit Memory Device with Delayed Write Command Processing

Memory Device Having a Configurable Oscillator for Refresh Operation

Integrated Circuit Memory Device Having Delayed Write Capability