Memory system having delayed write timing

Abstract

A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to electronic systems for data storage and retrieval. More particularly, the invention is directed toward improved methods and structures for memory devices.

2. Description of the Related Art

In any engineered design there are compromises between cost and performance. The present invention introduces novel methods and structures for reducing the cost of memory devices while minimally compromising their performance. The description of the invention requires a significant amount of background including: application requirements, memory device physical construction, and memory device logical operation.

Memory device application requirements can be most easily understood with respect to memory device operation. FIG. 1 shows the general organization of a memory device. Memory device 101 consists of a core 102 and an interface 103. The core is responsible for storage of the information. The interface is responsible for translating the external signaling used by the interconnect 105 to the internal signaling carried on bus 104. The primitive operations of the core include at least a read operation. Generally, there are other operations required to manage the state of the core 102. For example, a conventional dynamic random access memory (DRAM) has at least write, precharge, and sense operations in addition to the read operation.

For purposes of illustrating the invention a conventional DRAM core will be described. FIG. 2 is a block diagram of a conventional DRAM core 102. Since the structure and operation of a conventional DRAM core is well known in the art only a brief overview is presented here.

A conventional DRAM core 202 mainly comprises storage banks 211 and 221, row decoder and control circuitry 210, and column data path circuit comprising column amplifiers 260 and column decoder and control circuitry 230. Each of the storage banks comprises storage arrays 213 and 223 and sense amplifiers 212 and 222.

There may be many banks, rather than just the two illustrated. Physically the row and column decoders may be replicated in order to form the logical decoder shown in FIG. 2. The column i/o lines 245 may be either bidirectional, as shown, or unidirectional, in which case separate column i/o lines are provided for read and write operations.

The operation of a conventional DRAM core is divided between row and column operations. Row operations control the storage array word lines 241 and the sense amplifiers via line 242. These operations control the movement of data from the selected row of the selected storage array to the selected sense amplifier via the bit lines 251 and 252. Column operations control the movement of data from the selected sense amplifiers to and from the external data connections 204d and 204e.

Device selection is generally accomplished by one of the following choices:

• • matching an externally presented device address against an internally stored device address;
  • requiring separate operation control lines, such as RAS and CAS, for each set of memory devices that are to be operated in parallel; and
  • providing at least one chip select control on the memory device.

FIG. 3 illustrates the timing required to perform the row operations of precharge and sense. In their abstract form these operations can be defined as

• • precharge(device, bank)—prepare the selected bank of the selected device for sensing; and
  • sense(device, bank, row)—sense the selected row of the selected bank of the selected device.

The operations and device selection arguments are presented to the core via the PRECH and SENSE timing signals while the remaining arguments are presented as signals which have setup and hold relationships to the timing signals. Specifically, as shown in FIGS. 2-4, PRECH and PRECHBANK form signals on line 204a in which PRECHBANK presents the “bank” argument of the precharge operation, while SENSE, SENSEBANK and SENSEROW form signals on line 204b in which SENSEBANK and SENSEROW present the “bank” and “row” arguments, respectively, for the sense operation. Each of the key primary row timing parameters, t_RP, t_RAS,min, and t_RCD can have significant variations between devices using the same design and across different designs using the same architecture.

FIG. 5 and FIG. 6 illustrate the timing requirements of the read and write operations, respectively. These operations can be defined abstractly as:

• • data=read(device, bank, column)—transfer the data in the subset of the sense amplifiers specified by “column” in the selected “bank” of the selected “device” to the READDATA lines; and
  • write (device, bank, column, mask, data)—store the data presented on the WRITEDATA lines into the subset of the sense amplifiers specified by “column” in the selected “bank” of the selected “device”; optionally store only a portion of the information as specified by “mask”.

More recent conventional DRAM cores allow a certain amount of concurrent operation between the functional blocks of the core. For example, it is possible to independently operate the precharge and sense operations or to operate the column path simultaneously with row operations. To take advantage of this concurrency each of the following groups may operate somewhat independently:

• • PRECH and PRECHBANK on lines 204a;
  • SENSE, SENSEBANK, and SENSEROW on lines 204b;
  • COLCYC 204f on line, COLLAT and COLADDR on lines 204g, WRITE and WMASK one lines 204c, READDATA on line 204d, and WRITEDATA on line 204.

There are some restrictions on this independence. For example, as shown in FIG. 3, operations on the same bank observe the timing restrictions of t_RP and t_RAS,min. If accesses are to different banks, then the restrictions of FIG. 4 for t_SS and t_PP may have to be observed.

The present invention, while not limited by such values, has been optimized to typical values as shown in Table 1.

TABLE 1
Typical Core Timing Values
Symbol   Value (ns)
tRP      20
tRAS,Min 50
tRCD     20
tPP      20
tSS      20
tPC      10
tDAC     7

FIG. 7 shows the permissible sequence of operations for a single bank of a conventional DRAM core. It shows the precharge 720, sense 721, read 722, and write 723, operations as nodes in a graph. Each directed arc between operations indicates an operation which may follow. For example, arc 701 indicates that a precharge operation may follow a read operation.

The series of memory operations needed to satisfy any application request can be covered by the nominal and transitional operation sequences described in Table 2 and Table 3. These sequences are characterized by the initial and final bank states as shown in FIG. 8.

The sequence of memory operations is relatively limited. In particular, there is a universal sequence:

• • precharge,
  • sense,
  • transfer (read or write), and
  • close.

In this sequence, close is an alternative timing of precharge but is otherwise functionally identical. This universal sequence allows any sequence of operations needed by an application to be performed in one pass through it without repeating any step in that sequence. A control mechanism that implements the universal sequence can be said to be conflict free. A conflict free control mechanism permits a new application reference to be started for every minimum data transfer. That is, the control mechanism itself will never introduce a resource restriction that stalls the memory requester. There may be other reasons to stall the memory requestor, for example references to different rows of the same bank may introduce bank contention, but lack of control resources will not be a reason for stalling the memory requester

TABLE 2
Nominal Transactions
Initial	Final
Bank State	Bank State	Transaction Type	Operations Performed
closed	closed	empty	sense,
			series of column
			operations,
			precharge
open	open	miss	precharge,
			sense,
			series of column
			operations
		hit	series of column
			operations

TABLE 3
Transitional Transactions
Initial	Final
Bank State	Bank State	Transaction Type	Operations Performed
closed	open	empty	sense,
			<series of column
			operations>(optional)
open	closed	miss	<precharge,
			sense,
			series of column
			operations>(optional),
			precharge
		hit	<series of column
			operations>
			(optional),
			precharge

Memory applications may be categorized as follows:

• • main memory—references generated by a processor, typically with several levels of caches;
  • graphics—references generated by rendering and display refresh engines; and
  • unified—combining the reference streams of main memory and graphics.

Applications may also be categorized by their reference stream characteristics. According to the application partition mentioned above reference streams can be characterized in the following fashion:

• • First, main memory traffic can be cached or uncached processor references. Such traffic is latency sensitive since typically a processor will stall when it gets a cache miss or for any other reason needs data fetched from main memory. Addressing granularity requirements are set by the transfer size of the processor cache which connects to main memory. A typical value for the cache transfer size is 32 bytes. Since multiple memory interfaces may run in parallel it is desirable that the memory system perform well for transfer sizes smaller than this. Main memory traffic is generally not masked; that is, the vast bulk of its references are cache replacements which need not be written at any finer granularity than the cache transfer size.
  • Another type of reference stream is for graphics memory. Graphics memory traffic tends to be bandwidth sensitive rather than latency sensitive. This is true because the two basic graphics engines, rendering and display refresh, can both be highly pipelined. Latency is still important since longer latency requires larger buffers in the controller and causes other second order problems. The ability to address small quanta of information is important since typical graphics data structures are manipulated according to the size of the triangle being rendered, which can be quite small. If small quanta cannot be accessed then bandwidth will be wasted transferring information which is not actually used. Traditional graphics rendering algorithms benefit substantially from the ability to mask write data; that is, to merge data sent to the memory with data already in the memory. Typically this is done at the byte level, although finer level, e.g. bit level, masking can sometimes be advantageous.

As stated above, unified applications combine the characteristics of main memory and graphics memory traffic. As electronic systems achieve higher and higher levels of integration the ability to handle these combined reference streams becomes more and more important.

Although the present invention can be understood in light of the previous application classification, it will be appreciated by those skilled in the art that the invention is not limited to the mentioned applications and combinations but has far wider application. In addition to the specific performance and functionality characteristics mentioned above it is generally important to maximize the effective bandwidth of the memory system and minimize the service time. Maximizing effective bandwidth requires achieving a proper balance between control and data transport bandwidth. The control bandwidth is generally dominated by the addressing information delivered to the memory device. The service time is the amount of time required to satisfy a request once it is presented to the memory system. Latency is the service time of a request when the memory system is otherwise devoid of traffic. Resource conflicts, either for the interconnect between the requester and the memory devices, or for resources internal to the memory devices such as the banks, generally determine the difference between latency and service time. It is desirable to minimize average service time, especially for processor traffic.

The previous section introduced the performance aspects of the cost-performance tradeoff that is the subject of the present invention. In this section the cost aspects are discussed. These aspects generally result from the physical construction of a memory device, including the packaging of the device.

FIG. 9 shows the die of a memory device 1601 inside of a package 1620. For typical present day device packages, the bond pads, such as 1610, have center to center spacing significantly less than the pins of the device, such as 1640. This requires that there be some fan-in from the external pins to the internal bonding pads. As the number of pads increases the length of the package wiring, such as 1630, grows. Observe that elements 1630 and 1640 are alternately used to designate package wiring.

There are many negative aspects to the increase in the length of the package wiring 1640, including the facts that: the overall size of the package increases, which costs more to produce and requires more area and volume when the package is installed in the next level of the packaging hierarchy, such as on a printed circuit board. Also, the stub created by the longer package wiring can affect the speed of the interconnect. In addition, mismatch in package wiring lengths due to the fan-in angle can affect the speed of the interconnect due to mismatched parasitics.

The total number of signal pins has effects throughout the packaging hierarchy. For example, the memory device package requires more material, the next level of interconnect, such as a printed circuit board, requires more area, if connectors are used they will be more expensive, and the package and die area of the master device will grow.

In addition to all these cost concerns based on area and volume of the physical construction another cost concern is power. Each signal pin, especially high speed signal pins, requires additional power to run the transmitters and receivers in both the memory devices as well as the master device. Added power translates to added cost since the power is supplied and then dissipated with heat sinks.

The memory device illustrated in FIG. 10 uses techniques typical of present day memory devices. In this device 1701, a single shared command bus 1710 in conjunction with the single address bus 1720 and mask bus 1730 is used to specify all of the primitive operations comprising precharge, sense, read, and write in addition to any other overhead operations such as power management.

FIG. 11 illustrates the operation of the memory device of FIG. 10. The illustrated reference sequence, when classified according to Table 2 and the universal sequence previously described comprises:

• • write empty—sense 1851, write 1853 with mask 1871, data 1881, close(precharge) 1861;
  • write miss—precharge 1852, sense 1854, write 1856 with mask 1872, data 1882;
  • read hit—read 1857, tristate control 1873, data 1883; and
  • transitional write miss—precharge 1855, sense 1858, write 1859, mask 1874, data 1884, close(precharge) 1862.

In FIG. 11 each box represents the amount of time required to transfer one bit of information across a pin of the device.

In addition to illustrating a specific type of prior art memory device, FIG. 11 can be used to illustrate a number of techniques for specifying data transfers. One prior art technique uses an internal register to specify the number of data packets transferred for each read or write operation. When this register is set to its minimum value and the reference is anything besides a hit then the device has insufficient control bandwidth to specify all the required operations while simultaneously keeping the data pins highly utilized. This is shown in FIG. 11 by the gaps between data transfers. For example there is a gap between data a, 1881 and data b, 1882. Even if sufficient control bandwidth were provided some prior art devices would also require modifications to their memory cores in order to support high data pin utilization.

The technique of specifying the burst size in a register makes it difficult to mix transfer sizes unless the burst size is always programmed to be the minimum, which then increases control overhead. The increase in control overhead may be so substantial as to render the minimum burst size impractical in many system designs.

Regardless of the transfer burst size, the technique of a single unified control bus, using various combinations of the command pins 1810, address pins 1820, and mask pins 1830 places limitations on the ability to schedule the primitive operations. A controller which has references in progress that are simultaneously ready to use the control resources must sequentialize them, leading to otherwise unnecessary delay.

Read operations do not require masking information. This leaves the mask pins 1830 available for other functions. Alternately, the mask pins during read operations may specify which bytes should actually be driven across the pins as illustrated by box 1873.

Another technique is an alternative method of specifying that a precharge should occur by linking it to a read or write operation. When this is done the address components of the precharge operation need not be respecified; instead, a single bit can be used to specify that the precharge should occur. One prior art method of coding this bit is to share an address bit not otherwise needed during a read or write operation. This is illustrated by the “A-Prech” boxes, 1861 and 1862.

FIG. 12 shows a sequence of four read references each comprising all the steps of the universal sequence. Although the nominal transactions of Table 2 do not require the multiple precharge steps of the universal sequence it is useful to examine how well a device handles the universal sequence in order to understand its ability to support mixed empty and miss nominal transactions, as well as the transitional transactions of Table 3. As can be seen, the data pins are poorly utilized. This indicates that control contention will limit the ability of the device to transfer data for various mixes of application references. The utilization of the data pins could be improved by making the burst length longer. However, the applications, such as graphics applications, require small length transfers rather than large ones.

Another technique makes the delay from write control information to data transfer different from the delay of read control information to data transfer. When writes and reads are mixed, this leads to difficulties in fully utilizing the data pins.

Thus, current memory devices have inadequate control bandwidth for many application reference sequences. Current memory devices are unable to handle minimum size transfers. Further, current memory devices utilize the available control bandwidth in ways that do not support efficient applications. Current memory devices do not schedule the use of the data pins in an efficient manner. In addition, current memory devices inefficiently assign a bonding pad for every pin of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a known memory structure architecture.

FIG. 2 illustrates a known DRAM core structure.

FIG. 3 illustrates Row Access Timing to a single bank in accordance with the prior art.

FIG. 4 illustrates Row Access Timing to different banks in accordance with the prior art.

FIG. 5 illustrates Column Read Timing in accordance with the prior art.

FIG. 6 illustrates Column Write Timing in accordance with the prior art.

FIG. 7 illustrates operation sequences for a conventional core DRAM.

FIG. 8 illustrates initial and final bank states associated with a memory operation in accordance with the prior art.

FIG. 9 illustrates a semiconductor packaging structure utilized in accordance with the prior art.

FIG. 10 illustrates DRAM interface signals in accordance with the prior art.

FIG. 11 illustrates a command control sequence in accordance with the prior art.

FIG. 12 illustrates a unified control universal read sequence in accordance with an embodiment of the invention.

FIG. 13 illustrates a unified control universal read sequence with mask precharge in accordance with an embodiment of the invention.

FIG. 14 illustrates a unified control universal write sequence with mask precharge in accordance with an embodiment of the invention.

FIG. 15 illustrates a unified control universal read write sequence with mask precharge in accordance with an embodiment of the invention.

FIG. 16 illustrates a column access block diagram with no delayed write in accordance with an embodiment of the invention.

FIG. 17 illustrates timing operations associated with a write command of an embodiment of the invention.

FIG. 18 illustrates timing operations associated with a read command of an embodiment of the invention.

FIG. 19 illustrates mixed read and write timing in accordance with an embodiment of the invention.

FIG. 20 illustrates a column access with a delayed write in accordance with an embodiment of the invention.

FIG. 21 illustrates mixed read and write timing in accordance with an embodiment of the invention.

FIG. 22 illustrates a unified control universal read and write sequence with mask precharge and delayed write in accordance with the invention.

FIG. 23 illustrates a split control universal read write sequence with mask precharge and delayed write in accordance with an embodiment of the invention.

FIG. 24 illustrates a cost optimized highly concurrent memory in accordance with the invention.

FIG. 25 illustrates a control packet format for encoding the sense operation on the primary control lines in accordance with an embodiment of the invention.

FIG. 26 illustrates a control packet format for encoding the precharge operation on the primary control lines in accordance with an embodiment of the invention.

FIG. 27 illustrates a packet format when masking is not used on the secondary control lines of the invention.

FIG. 28 illustrates a packet format when masking is used on the secondary control lines of the invention.

FIG. 29 illustrates a data block timing diagram for data packets transmitted on data wires of the invention.

FIG. 30 illustrates a read hit in accordance with an embodiment of the invention.

FIG. 31 illustrates an empty read in accordance with an embodiment of the invention.

FIG. 32 illustrates a read miss in accordance with an embodiment of the invention.

FIG. 33 illustrates a write hit in accordance with an embodiment of the invention.

FIG. 34 illustrates an empty write in accordance with an embodiment of the invention.

FIG. 35 illustrates a write miss in accordance with an embodiment of the invention.

FIG. 36 illustrates reads in accordance with an embodiment of the invention.

FIG. 37 illustrates empty byte masked writes in accordance with an embodiment of the invention.

FIG. 38 illustrates byte masked write hits in accordance with an embodiment of the invention.

FIG. 39 illustrates byte masked write misses in accordance with an embodiment of the invention.

FIG. 40 illustrates reads or unmasked writes in accordance with an embodiment of the invention.

FIG. 41 illustrates universal byte masked writes in accordance with an embodiment of the invention.

FIG. 42 illustrates reads or unmasked writes in accordance with an embodiment of the invention.

FIG. 43 illustrates reads or masked writes or unmasked writes in accordance with an embodiment of the invention.

FIG. 44 illustrates reads and unmasked writes in accordance with an embodiment of the invention.

FIG. 45 illustrates transfers using a primary control packet for sense and precharge in accordance with an embodiment of the invention.

FIG. 46 illustrates a memory block constructed in accordance with an embodiment of the invention.

FIG. 47 illustrates DRAM refresh operations utilized in connection with an embodiment of the invention.

FIG. 48 illustrates isolation pins without accompanying pads in accordance with an embodiment of the invention.

FIG. 49 illustrates the transport of auxiliary information in accordance with an embodiment of the invention.

FIG. 50 illustrates framing of the CMD for processing by the auxiliary transport unit in accordance with an embodiment of the invention.

Like reference numerals refer to corresponding parts throughout the drawings.

DESCRIPTION OF EMBODIMENTS

FIG. 13 shows a timing diagram according to an embodiment of the present invention in which the Mask pins 2030 carry a precharge specification rather than either the write mask information or the tristate control information, as shown in connection with FIG. 12. This use of the Mask pins need not be exclusive. There are multiple ways in which to indicate how the information presented on the Mask pins is to be used. For example:

• • in one embodiment according to the present invention, a register within the device specifies whether the mask pins are to be used for masking, tristate control, or precharge control;
  • in another embodiment according to the present invention, the encoding of the command pins is extended to specify, on a per operation basis, how the mask pins are to be used; and
  • in another embodiment according to the present invention, a register bit indicates whether tristate control is enabled or not and, in the case it is not enabled, an encoding of the command pins indicates if a write is masked or not; in this embodiment all reads and unmasked writes may use the Mask pins to specify a precharge operation while masked writes do not have this capability since the Mask pins are used for mask information

There are many alternatives for how to code the precharge information on the mask pins. In one embodiment in which there are two mask pins and the memory device has two banks, one pin indicates whether an operation should occur and the other pin indicates which bank to precharge. In an alternative embodiment, in which the minimum data transfer requires more than one cycle, more banks are addressed by using the same pins for more than one cycle to extend the size of the bank address field.

Using the mask pins to specify a precharge operation and the associated bank address requires another way of specifying the device argument. In one embodiment the device is specified in some other operation. For example, the precharge specified by the mask pins shares device selection with a chip select pin that also conditions the main command pins. In another embodiment, additional control bandwidth is added to the device. For example, an additional chip select pin is added for sole use by the recoded mask pin precharge. In yet another example of using additional control bandwidth in which the minimum data transfer requires more than one cycle, the device address is coded on the additional bits, the device address being compared to an internal device address register.

In FIG. 13 it can be seen that the data pins are better utilized. For example, the offset between data block 1982 and 1983 in FIG. 12 is reduced from 4 units of time to the 2 units of time between data blocks 2082 and 2083 of FIG. 13. This is accomplished because the precharge specification has been moved from the primary command pins, 2010, to the mask pins 2030 so there is more time available on the command pins to specify the sense and read or write operations.

DELAYING WRITE DATA

FIG. 14 shows the timing of the universal write sequence in an embodiment according to the present invention, when the Mask pins are used for the precharge step. The offset from data block 2182 to data block 2183 is two units of time just as in the read sequence shown in FIG. 13. However, the offset from the use of the command pins to the use of the data pins is shown as zero for the write case but three for the read case. As can be seen in FIG. 15, when these sequences are combined to produce a sequence that has both reads and writes, there is a substantial gap between the write data and the read data as can be seen by the delay between data 2282 and data 2283. Delaying the write data so that the offset from control information to data is the same, independent of whether the transfer is a read or a write, reduces or eliminates the delay.

FIG. 16 shows the column access path of a memory device in an embodiment of the invention that does not delay write data with respect to read data. In FIG. 16, the delay from external control 2304 to internal column control 2306 is identical whether the access is a read or a write. As can be seen from FIG. 5 and FIG. 6, this means that the external data interconnect 2305 provides the data to the core prior to the write, while the external data interconnect is used after the core provides data for a read. In summary, a read uses resources in the order: (a) control interconnect 2304, (b) column i/o 2307, (c) data interconnect 2305. A write uses them in the order: (a) control interconnect 2304, (b) data interconnect 2305, (c) column i/o 2307.

This change in resource ordering gives rise to resource conflict problems that produce data bubbles when mixing reads and writes. The resource ordering of writes generally leads to the resource timing shown in FIG. 17. For example, a write uses resource as shown by block 2440, the data resource as shown by block 2450, and the column resource as shown by the block 2460. This resource timing minimizes the control logic and the latency of writing data into the memory core.

The read resource timing of FIG. 18, illustrates a minimum latency read via block 2540, column i/o block 2560, and data block 2550. When these timings are combined as shown in FIG. 19, a data bubble is introduced between blocks 2652 and 2653 of FIG. 19. This data bubble constitutes time during which the data pins are not being utilized to transfer data; the pins are inactive. Forcing the data pins to do nothing as a result of mixing reads and writes is a problem.

Note that the data bubble appears regardless of whether the write 2642 and the read 2643 are directed to the same or different memory devices on the channel. Further note that the delay from the control resource to the column i/o resource is identical for reads and writes. In view of this, it is impossible for the data resource timing to be identical for reads and writes.

Matching the timing of the write-use of the data resource to the read-use of the data resource avoids the problem stated above. Since the use of the data pins in a system environment has an intrinsic turnaround time for the external interconnect, the optimal delay for a write does not quite match the delay for a read. Instead, it should be the minimum read delay minus the minimum turnaround time. Since the turnaround delay grows as the read delay grows, there is no need to change the write control to data delay as a function of the memory device position on the channel.

FIG. 20 shows an embodiment of the invention having delayed write circuitry. The column access control information on line 2706 is delayed for writes relative to when the column control information is presented to the core for reads. FIG. 20 shows multiplexer 2712 which selects between the write delay block 2709 and the normal column control output of the interface. The interface controls the multiplexer depending upon whether the transfer is a read or a write. However, there are many embodiments of this mechanism. For example, a state machine could introduce new delaying state transitions when the transfer is a write.

FIG. 21 shows the operation of delaying the write to match the read in accordance with the present invention. In this figure, the delay from write control block 2842 to write data block 2852 is set to match the delay from read control 2843 block to read data 2853 block less the channel turnaround time. As long as different column data paths are used to perform the read column cycle and the write column cycle, the data bubble is reduced to the minimum required by channel turnaround requirements and is no longer a function of control or data resource conflicts.

Since write latency is not an important metric for application performance, as long as the write occurs before the expiration of t_RAS,MIN (so that it does not extend the time the row occupies the sense amplifiers, which reduces application performance), this configuration does not cause any loss in application performance, as long as the writes and reads are directed to separate column data paths.

Delayed writes help optimize data bandwidth efficiency over a set of bidirectional data pins. One method adds delay between the control and write data packets so that the delay between them is the same or similar as that for read operations. Keeping this pattern the same or similar for reads and writes improves pipeline efficiency over a set of bidirectional data pins, but at the expense of added complexity in the interface.

FIG. 22 shows that the offset between write data 2984 block and read data 2985 block has been reduced by 2 units of time, compared to the analogous situation of FIG. 15.

Split Control Resources

FIG. 22 shows less than full utilization of the data interconnect due to the overloaded use of the command pins 2910. The command pins can be partitioned so that these operations are delivered to the device in an independent fashion. The timing of such a control method is shown in FIG. 23 where the unified control has been partitioned into fields of control information, labeled primary field 3011 and secondary field 3012. Generally speaking the primary control pins can be used to control the sense operation while the secondary control pins control read or write operations. An embodiment of the present invention allows full utilization of the data pins and can transfer minimum size data blocks back-to-back, for any mix of reads or unmasked writes, for any mix of hits, misses, or empty traffic, to or from any device, any bank, any row, and any column address with only bank conflict, channel turnaround at the write-read boundaries, and 2nd order effects such as refresh limiting the data channel utilization. With the addition of more interconnect resources the writes could be masked or unmasked. Observe that FIG. 23 presumes that the memory device is designed for an interconnect structure that has zero turnaround delay between writes and reads.

FIG. 24 shows an embodiment of the invention that has separate control interconnect resources. In one embodiment it uses delayed writes. In another embodiment it can alternately specify either a masking or a precharge field, either singly or in conjunction with another field. In another embodiment it combines delayed writes and the masking versus precharge. In an alternative embodiment according to the present invention there are three methods for starting a precharge operation in the memory core:

• • in the sense operation field on the primary control lines 3104, as an alternative to the sense information;
  • in the mask field on the secondary control lines, 3105 as an alternative to the mask information; and
  • according to the device and bank addresses specified in a read or a write.

The benefit of the present invention according to a specific embodiment is shown in Table 4 and FIG. 25 and FIG. 26. Table 4 shows the specific logical pinout of the embodiment of FIG. 24 to be used for this illustrative purpose.

TABLE 4
High Performance Logical Pin Description
			FIG. 24
Name	Count	Description	Reference
Primary[2:0]	3	Primary request control	3104
Secondary[4:0]	5	Secondary request control	3105
DQA[8:0]	9	Low order data byte	3106
DQB[8:0]	9	High order data byte

FIG. 25 and FIG. 26 show two alternative control packet formats for encoding, respectively, the sense and precharge operations on the primary control lines. Table 5 defines the fields in the alternative formats of the primary control packet. The PD field selects a specific memory device. A combined field carries both the bank and row address arguments of the sense operation, as previously defined.

TABLE 5
Primary Control Packet Fields
Field     Description
PD4T      Device selector bit 4 True;
          for framing, device selection and broadcasting.
PD4F      Device selector bit 4 False;
          for framing, device selection and broadcasting.
PD[3:0]   Device selector, least significant bits.
AV        Activate row; also indicates format of packet.
PA[16:0]  Address; combining bank and row.
PB[5:0]   Bank address
POP[10:0] Opcode of the primary control packet.

FIG. 27 and FIG. 28 show two alternative control packet formats for encoding various operations on the secondary control lines. FIG. 27 shows the packet format when masking is not being performed while FIG. 28 shows the format when masking is being performed. Table 6 defines the fields in either format of the secondary control packet. Packet framing is accomplished via a framing bit. The M field is used to indicate which format of the packet is being presented as well as indicating whether write data being written to the core should be masked. The SO field indicates whether a read or write operation should be performed. Device selection for SO specified operations is accomplished according to the SD field which is compared against an internal register that specifies the device address. The SA field encodes the column address of a read or write operation. The SB field encodes the bank address of a read or write operation. If the SPC field indicates precharge, then the precharge operation uses the SD device and SB bank address. The SRC field is used for power management functions. The MA and MB fields provide a byte masking capability when the M field indicates masking. The XO, XD, and XB fields provide the capability to specify a precharge operation when the M field does not indicate masking. Note that, unlike the SPC field, this specification of a precharge has a fully independent device, XD, and bank address, XB, that is not related to the read or write operations.

FIG. 29 shows the format of the data packet transmitted on the data wires.

TABLE 6
Secondary Control Packet Fields
Field   Description
SD[4:0] Device selector for Column Operation
SS = 1  Start bit; for framing
M       Mask bit, indicates if mask format is being used
SO[1:0] Secondary Operation code
SPC     Precharge after possible Column Operation
SRC     Power management
SA[6:0] Address for Column Operation
SB[5:0] Bank for Column Operation
MA[7:0] Byte mask for lower order bytes
MB[7:0] Byte mask for higher order bytes
XD[4:0] Device selector for Extra Operation
XO[4:0] Extra Operation code
XB[5:0] Bank for Extra Operation

The operation of this embodiment can be most easily understood through various timing diagrams as shown in FIG. 30 through FIG. 45. These figures can be divided into several series, each of which depicts different aspects of this embodiment's operation:

• • FIG. 30 through FIG. 35 show a basic operation as an embodiment of the present invention, other operations can be thought of as compositions of these basic operations;
  • FIG. 36 through FIG. 39 show compositions of the basic operations but distinct from notions of the universal sequence;
  • FIG. 40 through FIG. 43 show operations according to the universal sequence, these figures demonstrate the ability of the embodiment to handle mixed read and write with mixed hit, miss, and empty traffic without control resource conflicts; and
  • FIG. 44 through FIG. 45 show operations according to the universal sequence demonstrating less control conflicts than the prior art. Other control scheduling algorithms are possible which seek to minimize other metrics, such as service time, with or without compromising effective bandwidth.

The nominal timings for the examples are shown in Table 7.

TABLE 7
Nominal Timings
Symbol   Value (ns)
tRP      20
tRAS,min 60
tRCD     20
tCAC     20

A description of each of the timing diagrams follows.

FIG. 30 shows a timing diagram for a nominal read hit. Recall that a nominal hit reference means that the beginning and final state of the addressed bank is open and that the appropriate row is already in the sense amplifiers of the addressed bank. In this case no row operation is required. The secondary control packet specifies the read operation, device address, bank address, and column address. Some time later, the read data is driven on the data pins. In an embodiment according to the present invention it as a constant time, later fixed by the design of the memory device.

FIG. 31 shows a timing diagram for a nominal read empty. Recall that a nominal empty reference means that the beginning and final state of the addressed bank is closed. In order to transfer data, the addressed bank is first sensed, and then, after t_RCD, the read operation takes place just as for the read hit of FIG. 30. Note that this particular example shows the precharge occurring using the primary control packet precharge mechanism. Alternately, other precharge mechanisms are used, since there are no other references contending for the control resources.

FIG. 32 shows a timing diagram for a nominal read miss. Recall that a nominal miss reference means that the beginning and final state of the addressed bank is open, but that the row currently sensed in the bank is not the one addressed by the application reference. In this case, a precharge operation occurs, followed by a sense operation, and finally a read operation that causes the proper data to be driven out on the data pins. Any precharge mechanisms can be used.

FIG. 33 shows a nominal write hit. The figure relates to a multistep write operation. Thus, there is a secondary control packet in order to get the transported data sent all the way into the memory core. This second secondary control packet provides a timing reference that indicates to the memory device that it is time to send the data to the core.

FIG. 34 shows a timing diagram for a nominal write empty. A write empty operation is a combination of the actions needed for a read empty and a write hit. First, a sense operation is performed, followed by a write operation, including the secondary control packet, followed by some precharge operation, although a primary precharge operation is shown.

FIG. 35 illustrates a timing diagram for a nominal write miss. Write miss operation is a combination of the actions needed for a read miss and a write hit. First, a precharge operation is invoked; a primary precharge operation is shown. A sense operation follows, along with the two secondary control packets needed to write the data all the way to the memory core.

The previous figures show how various application references can be decomposed into the memory operations. FIG. 36 illustrates how one of these isolated references can be used for a sequence of memory references. In FIG. 36 a sequence of nominal read empty references is shown. In this case the XO precharge operation is used to perform the close operation at the end of the sequence. The present invention thus provides another precharge mechanism that neither overloads the external control pin resources, nor adds logic to the memory device.

FIG. 37 shows timing for a series of nominal masked write empty references. In this case, the XO precharge operation is not available because those control pin resources are being used to supply the mask information. Instead, the SPC field is used in order to avoid bubbles, since the primary control pins are already committed to the series of sense operations. Presuming that the delay between sense and write operations is such that write read conflict problems are being avoided, as shown with the previous discussion on delayed writes, there is no real penalty for using the SPC field. This is different from reads, which would normally complete, and which desire to complete, sooner. This asymmetry between reads and writes leads to the cost reductions of the present invention by reducing required control bandwidth, while minimally impacting application performance.

FIG. 38 shows a series of nominal masked write hit references. Note that although two secondary control packets were required to fully write data into the memory core for an isolated reference the average number needed is about one.

FIG. 39 shows a timing diagram for a series of masked writes misses. In this example the SPC field is used to precharge the bank. Such a sequence is useful in a graphics application which varies the length of time it keeps any bank open depending upon the amount of rendering to be done. If more than one transfer is directed to the same row of the same bank of the same device then some of the SPC precharge operations and the corresponding sense operations can be removed. This is useful both to eliminate unnecessary (precharge, sense) power but also to reduce the effective number of independent banks required to sustain the effective bandwidth, even when bank conflicts might occur.

FIG. 40 shows a timing diagram for the universal sequence for minimum size transfers when the write traffic is not masked. In this case the XO precharge operation can be consistently used for the precharge operation which begins the universal sequence, while the SPC field is used for the close operation which ends the universal sequence. As can be seen, once the first reference has completed its sequence every reference behind it continues without any delays due to control resource constraints. The only delays are due to external interconnect turnaround delays. The processor cache miss traffic typically does not contain frequent masked write activity but is latency sensitive. Since it does not use the masking capability it can use the XO precharge capability.

FIG. 41 demonstrates the extra degree of freedom permitted when the transfer size per (sense, precharge) pair is twice the minimum transfer size. In this case some of the primary control bandwidth becomes available for precharge control. In this case the universal sequence can be implemented even for masked writes.

FIG. 42 shows a timing diagram for the universal sequence for reads and unmasked writes when the transfer size is twice the minimum per (precharge, sense) pair. In this case the precharge step of the universal sequence is scheduled with the primary packet precharge while the close step is scheduled with the XO precharge. In this case not only is there adequate control bandwidth but there is more scheduling freedom for each of the steps of the universal sequence compared to the minimum transfer size per (precharge, sense) pair case.

FIG. 43 shows a timing diagram for universal reads or masked writes or unmasked writes. In this case the precharge step of the universal sequence is still scheduled in the primary control packet but the close step is scheduled with the XO precharge operation. This reduces the scheduling flexibility compared to the unmasked case 24 but still permits full data pin utilization.

The previous figures demonstrate the conditions in which the universal sequence can be scheduled. The ability to schedule the universal sequence guarantees that there will not be any control conflicts which reduce available data transfer bandwidth. However, none of the nominal reference sequences actually requires two precharges to be scheduled. So there is generally adequate control bandwidth for various mixes of miss and empty traffic as shown in FIG. 44.

FIG. 45 shows a timing diagram for another scheduling alternative when the transfer size is twice the minimum per (precharge, sense) pair and the traffic consists of all empty references. In this case both the sense and precharge can be scheduled on the primary control pins.

FIG. 46 shows an alternative embodiment that includes all of the features of FIG. 24, but includes additional capability to initialize, read and write registers, and supply power control information to the memory device. The pinout of this embodiment is summarized in Table 8.

TABLE 8
Alternative High Performance Logical Pin Description
Name	Count	Type	Description	FIG. 46 Reference
CTM	2	RSL	Transmit Clock	5301
CTMN			(Clock To Master)
CFM	2	RSL	Receive Clock
CFMN			(Clock From Master)
Primary[2:0]	3	RSL	Primary request control	5305
Secondary[4:0]	5	RSL	Secondary request control	5305
DQA[8:0]	9	RSL	Low order data byte	5307
DQB[8:0]	9	RSL	High order data byte
SIO[1:0]	2	CMOS	Bidirectional serial in/out for	5302 and 5304
			device initialization, register
			ops, power mode control, and
			device reset. Used to form the
			SIO daisy chain.
SCK	1	CMOS	Serial clock for SIO and CMD	5303
			pins.
CMD	1	CMOS	Command input used for	5302
			power mode control,
			configuring SIO daisy chain,
			and framing SIO operations.

FIG. 47 shows the operation sequence for the alternative embodiment of FIG. 46. The refresh specific operations support a novel method of handling core refresh. These new core operations create the requirements for the Refresh and RefreshS operations coded in the primary control packet as shown in FIG. 46. In addition, various power control operations are added to the primary control packet.

FIG. 48 shows an embodiment of the physical construction in which not all of the pins of the memory device are connected to the bond pads of the die. These non-connected pins provide signal isolation and shielding, thus avoiding the expense of additional bond pads. For example, pin and internal conductor 5542 provides isolation for pin and internal conductors 5541 and 5543. In one embodiment the non-connected pins are signal returns, such as ground, which are adjacent to the connected pins.

According to an embodiment of the present invention the memory device of FIG. 46 has Auxiliary information 5302 transported in time according to FIG. 49. Auxiliary information 5302 includes a field to specify an auxiliary operation, a control register address in the memory device, and data to be read or written from or to the control register. AuxClock is the AuxClock signal to the Auxiliary Transport Unit 5308 and is used to receive information from the auxiliary connections 5302 in FIG. 46. Since Auxiliary Transport Unit 5308 operates to reset or initialize the memory device, the unit need only operate slowly. Accordingly, information is framed by the CMD signal, which can be a portion of the auxiliary connections 5302, and received on the Auxln signal as a serial bit stream. The format of the bit stream is shown in the tables below. As can be noted from Table 9 there are sixteen clock cycles during which a packet of information is received or obtained from the Auxiliary Transport Unit. The Aux information fields are the SOP[3:0] field and the SDEV[4:0] field for the SRQ packet. The SA packet has field SA[11:0], the SINT packet has a field of all zeros and the SD packet has SD[15:0]. In this embodiment of the present invention, the SRQ, SA, SINT and SD packets are received or obtained from the Auxiliary Transport unit in the order listed, unless only the SRQ packet is needed, in which case the other packets are not sent. The functions of each of the fields in the packets is tabulated in Table 10.

TABLE 9
Control Register Packet Formats
AuxClock	SRQ packet	SA packet	SINT	SD
0	rsrv	rsrv	0	SD15
1	rsrv	rsrv	0	SD14
2	rsrv	rsrv	0	SD13
3	rsrv	rsrv	0	SD12
4	rsrv	SA11	0	SD11
5	rsrv	SA10	0	SD10
6	SOP3	SA9	0	SD9
7	SOP2	SA8	0	SD8
8	SOP1	SA7	0	SD7
9	SOP0	SA6	0	SD6
10	SBC	SA5	0	SD5
11	SDEV4	SA4	0	SD4
12	SDEV3	SA3	0	SD3
13	SDEV2	SA2	0	SD2
14	SDEV1	SA1	0	SD1
15	SDEV0	SA0	0	SD0

TABLE 10
Field Description for Control Register Packets
Field             Description
rsrv              Reserved
SOP3 . . . SOP0   Serial opcode. Specifies command for control register transaction.
                  0000 - SRD. Serial read of control register {SA11 . . . SA0} of
                  memory device {SDEV4 . . . SDEV0}.
                  0001 - SWR. Serial write of control register {SA11 . . . SA0} of
                  memory device {SDEV4..SDEV0}.
                  0010 - SETR. Set Reset bit, all control registers assume their reset
                  values.
                  0011 - CLRR. Clear Reset bit, all control registers retain their
                  reset values.
                  0100 - SETF. Set fast (normal) clock mode for the clock circuitry
SDEV4 . . . SDEV0 Serial device field.
SBC               Serial broadcast. When set, memory device ignores
                  {SDEV4 . . . SDEV0} serial device field
SA11 . . . SA0    Serial address. Selects which control register of the selected
                  memory device is read or written.
SD15 . . . SD0    Serial data. The 16 bits of data written to or read from the selected
                  control register of the selected memory device.

As is shown in Table 10, the memory device is selected by the SDEV field and the SOP field determines the Auxiliary Operation to be performed by the Register Operation Unit 5309 in FIG. 46. The Auxiliary Transport Unit also supports the initialization of the memory device because the Auxiliary Transport Unit itself does not require initialization. This function is shown in FIG. 49. In this diagram the CMD signal received by the Auxiliary Transport Unit has different framing information to indicate that an initialization packet follows. This causes all of the memory devices which are connected together on the same external connections in FIG. 46 to break apart a daisy chain connection formed from AuxIn through AuxOut to AuxIn of the next memory device in the chain as the initialization packet passes through the daisy chain. Next, the first memory device in the chain receives a device identification field from the Auxiliary Transport unit into one of its control registers. This field serves to identify the device for future Auxiliary Transport Operations. After the memory device has its control registers configured properly, the device field register is written again to change a bit, causing the first device in the chain to pass the Auxiliary information it receives to the next device in the chain. The sequence is repeated until all of the memory devices have their control registers properly configured and each device has an unique identification.

According to an embodiment of the present invention the memory device of FIG. 46 receives power control information, specifying a change in the power mode of the memory device. While power control operations such as Powerdown and Nap are encoded into the precharge packets in one embodiment according to the present invention, other power control operations, such as ExitToNormal and ExitToDrowsy come in through the Auxiliary Transport Unit because the other units in FIG. 46 are not operational due to their reduced power state and because the Auxiliary Transport Unit operates relatively slowly compared to, for example, the Transfer Units, and so does not require much power while the other units are in their reduced power state. These Exit operations may be performed according to FIG. 50. FIG. 50 shows a different framing by the CMD signal so that the Auxiliary Transport Unit can recognize the ExitToNormal or ExitToDrowsy request. According to the timing diagram, when a memory device receives a CMD signal 01 with 0 on the falling edge of AuxClock and 1 on the rising edge of AuxClock, the memory device will exit either the power down state or the nap state (Power State A in the timing diagram) and move to a new power state (Power State B in the diagram), depending on the state of the AuxIn Signal Line. If the AuxIn line is a 1, the memory device will exit to the normal state and if the AuxIn line is a 0 the memory device will exit to the drowsy state. In other embodiments, the meaning of the AuxIn bits is reversed. The device that is targeted for the ExitToNormal or ExitToDrowsy operation is received by the Auxiliary Transport Unit 5308 on the data input field via path 5307 of the memory device in FIG. 46.

In an alternate embodiment, each memory device receives a different CMD signal, one for each device, rather than using the data input field via path 5307 to identify the device for a ExitToNormal or ExitToDrowsy operation.

The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. In other instances, well known circuits and devices are shown in block diagram form in order to avoid unnecessary distraction from the underlying invention. Thus, the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, obviously many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims

1. A system comprising: a first set of interconnect resources to convey: a sense command; andafter the sense command, a write command that specifies a write operation;a second set of interconnect resources to convey: a row address that identifies row of a memory array to sense in response to the sense command; andafter the row address, a column address that identifies a column location of the row;a third set of interconnect resources to convey data; anda memory device comprising: a memory core including a plurality of memory cells;a first set of pins coupled to the first set of interconnect resources, the first set of pins to receive the sense command and the write command, wherein, after a first delay time transpires from when the write command is received at the first set of pins, the memory device applies a control signal to convey a plurality of data bits to the column location, in response to the write command;a second set of pins coupled to the second set of interconnect resources, the second set of pins to receive the row address and the column address; anda third set of pins coupled to the third set of interconnect resources, the third set of pins to receive the plurality of data bits after a second delay time has transpired from when the write command is received at the second set of pins.

2. The system of claim 1, wherein: the first set of pins receives a read command; andthe third set of pins output read data to the third set of interconnect resources in response to the read command, wherein the read data is output after a third delay time has transpired from when the read command is received by the first set of pins, wherein the second delay time is based on the third delay time.

3. The system of claim 2, wherein the second delay time is based on the third delay time such that the second delay time is a channel turnaround time less than the third delay time.

4. The system of claim 2, wherein the memory device further comprises a pin to receive a clock signal, wherein, in response to the read command, each pin of the third set of pins outputs a first bit of the read data at a rising edge of the clock signal and a second bit of the read data at a falling edge of the clock signal.

5. The system of claim 2, wherein the memory device further comprises a pin to receive a clock signal, wherein, in response to the write command, each pin of the third set of pins receives two data bits of the plurality of data bits during a clock cycle of the clock signal.

6. A system comprising: a first interconnect to convey a clock signal;a second interconnect to convey: a write command that specifies storage of write data in a memory core during a write operation; anda read command that specifies output of read data accessed from the memory core;a third interconnect to convey the write data and the read data; andan integrated circuit memory device comprising: a pin coupled to the first interconnect, the pin to receive the clock signal from the first interconnect;a first plurality of pins coupled to the second interconnect, the first plurality of pins to receive the write command from the second interconnect, wherein, in response to the write command a write operation is initiated in the integrated circuit memory device after a first predetermined delay time transpires from when the write command is received at the first plurality of pins; anda second plurality of pins coupled to the third interconnect, the second plurality of pins to receive the write data after a second predetermined delay time has transpired from when the write command is received at the first plurality of pins, and wherein, in response to the read command, each pin of the second plurality of pins conveys to the third interconnect, a first bit of the read data at a rising edge of the clock signal, and a second bit of the read data at a falling edge of the clock signal.

7. The system of claim 6, wherein: the second interconnect conveys an activate command;the first plurality of pins receives the activate command; andwherein the integrated circuit memory device further comprises: a memory core including a plurality of memory cells; anda third plurality of pins to receive a row address, a first column address and a second column address, wherein: the row address identifies a row of memory cells of the plurality of memory cells;the activate command specifies that the memory device sense the row of memory cells identified by the row address;the first column address identifies a column location at which to store the write data; andthe second column address identifies a column location at which to obtain the read data.

8. The system of claim 7, wherein the first plurality of pins receives the activate command during a first command cycle, the write command during a second command cycle and the read command during a third command cycle; andthe third plurality of pins receives the row address during the first command cycle, the first column address during the second command cycle, and the third column address during the third command cycle.

9. The system of claim 6, wherein control information is applied to initiate the write operation after the first predetermined delay time transpires from when the write command is received at the first plurality of pins.

10. A system comprising: a first interconnect to convey a clock signal;a second interconnect to convey: a write command that specifies storage of write data in a memory core during a write operation; anda read command that specifies output of read data accessed from the memory core;a third interconnect to convey the write data and the read data; andan integrated circuit memory device comprising: a pin coupled to the first interconnect, the pin to receive the clock signal from the first interconnect;a first set of pins coupled to the second interconnect, the first set of pins to receive the write command and the read command from the second interconnect, wherein, in response to the write command, the integrated circuit memory device applies control information to initiate the write operation, wherein the control information is applied after a first predetermined delay time transpires from when the write command is received at the first set of pins; anda second set of pins coupled to the third interconnect, the second set of pins to receive the write data after a predetermined write delay time has transpired from when the write command is received at the first set of pins, the second set of pins to provide the read data to the third interconnect after a predetermined read delay time transpires from when the read command is received at the first set of pins, wherein the predetermined write delay time is based on the predetermined read delay time.

11. The system of claim 10, wherein the predetermined write delay time is a channel turnaround time less than the predetermined read delay time.

12. The system of claim 10, wherein: the second interconnect conveys an activate command;the first set of pins receives the activate command; andwherein the memory core comprises memory cells, and the integrated circuit memory device further comprises a third set of pins to receive a row address, a first column address and a second column address, wherein: the activate command specifies that the memory device sense a row of the memory cells identified by the row address;the first column address identifies a column location at which to store the write data; andthe second column address identifies a column location at which to obtain the read data.

13. The system of claim 12, wherein the first set of pins receives, from the second interconnect, the activate command during a first command cycle, the write command during a second command cycle and the read command during a third command cycle; andthe third set of pins receives the row address during the first command cycle, the first column address during the second command cycle, and the third column address during the third command cycle.

14. The system of claim 10, wherein the first set of pins receives, from the second interconnect, an activate command, a row address, a first column address and a second column address, wherein the activate command specifies that the memory device sense a row of memory cells in the memory core, the first column address identifies a column location at which to store the write data; and the second column address identifies a column location at which to obtain the read data, wherein: the activate command and the row address are included in a first packet;the write command and the first column address are included in a second packet; andthe read command and the third column address are included in a third packet.

15. The system of claim 14, wherein: the first packet is conveyed over a first portion of the second interconnect;the second packet is conveyed over a second portion of the second interconnect; andthe third packet is conveyed over the second portion of the second interconnect.

16. A system comprising: a first interconnect to convey a clock signal;a second interconnect to convey: a write command that specifies storage of write data in a memory core during a write operation; anda read command that specifies output of read data accessed from the memory core;a third interconnect to convey the write data and the read data;an integrated circuit memory device comprising: a pin coupled to the first interconnect, the pin to receive the clock signal from the first interconnect;a first set of pins coupled to the second interconnect, the first set of pins to receive the write command from the second interconnect, wherein, in response to the write command, the write operation is initiated in the integrated circuit memory device after a predetermined delay time transpires; anda second set of pins coupled to the third interconnect, the second set of pins to receive the write data, each pin of the second set of pins that receives write data to receive a first bit of the write data on a rising edge of the clock signal and a second bit of the write data on a falling edge of the clock signal, the second set of pins to provide the read data to the third interconnect, each pin of the second set of pins to provide a first bit of the read data on a rising edge of the clock signal and a second bit of the read data on a falling edge of the clock signal.

17. The system of claim 16, wherein: the second set of pins receives the write data after a write delay time has transpired from when the write command is received at the first set of pins; andwherein the second set of pins provides the read data after a read delay time transpires from when the read command is received at the first set of pins, wherein the write delay time is based on the read delay time, such that the write delay time is a channel turnaround time less than the read delay time.

18. A system comprising: a first set of interconnect resources to convey: a sense command;after conveying the sense command, a write command that specifies a write operation; andafter conveying the write command, a read command that specifies a read operation;a second set of interconnect resources to convey a row address that identifies a row of a memory array to sense in response to the sense command;a third set of interconnect resources to convey data bits; anda memory device comprising: a memory core including a plurality of memory cells;a first set of pins coupled to the first set of interconnect resources, the first set of pins to receive the sense command, the write command, and the read command, wherein, in response to the write command and after a first delay time transpires from when the write command is received, the memory device asserts a control signal to convey a plurality of data bits to the row identified by the row address;a second set of pins coupled to the second set of interconnect resources, the second set of pins to receive the row address; anda third set of pins coupled to the third set of interconnect resources, the third set of pins to receive the plurality of data bits after a second delay time has transpired from when the write command is received at the first set of pins, the third set of pins to output read data in response to the read command, wherein the read data is output after a third delay time has transpired from when the read command is received at the first set of pins, wherein the second delay time is based on the third delay time.

19. The system of claim 18, wherein the second delay time is based on the third delay time such that the second delay time is a channel turnaround time less than the third delay time.

20. The system of claim 18, wherein the memory device further comprises a plurality of sense amplifiers to sense, in response to the sense command, data stored in the row identified by the row address, and wherein the plurality of memory cells are dynamic memory cells.

21. A method of operation in a system that includes a memory device having a memory core, the method comprising: conveying, to the memory device and over a first interconnect, a sense command that specifies that the memory device activate a row of memory cells in the memory core;conveying, to the memory device and over a second interconnect, a row address that identifies the row;conveying, to the memory device and over the first interconnect, a write command that specifies that the memory device receive write data, wherein, in response to the write command and after a first delay time transpires from when the write command is received by the memory device, the memory device asserts a control signal to store the write data in the row;conveying, to the memory device and over the first interconnect, a read command that specifies that the memory device output read data, wherein in response to the read command and after a second delay time transpires from when the read command is received by the memory device, the memory device outputs the read data; andconveying write data to the memory device, wherein the write data is conveyed after a third delay time has transpired from when the write command was conveyed to the memory device, wherein the third delay time is based on the second delay time.

22. The method of claim 21, further including: conveying, to the memory device and over the second interconnect, a first column address that identifies a location in the row in which to store the write data; andconveying, to the memory device and over the second interconnect, a second column address that identifies a location in the row in which to obtain the read data.

23. The method of claim 21, wherein the third delay time is based on the second delay time such that the third delay time is a channel turnaround time less than the second delay time.

24. The method of claim 21, wherein the sense command and the row address are conveyed to the memory device together during a clock cycle of a clock signal used in the system.

25. A method of operation in a system that includes a memory device having a memory core that includes a plurality of memory cells, the method comprising: conveying, to the memory device, a sense command that specifies that the memory device activate a row of memory cells of the plurality of memory cells;conveying, to the memory device, a row address that identifies the row;conveying, to the memory device, a bank address that identifies a bank of the memory core that contains the row;conveying, to the memory device, a write command that specifies that the memory device receive write data, wherein, in response to the write command, the memory device initiates a write operation after a first delay time transpires from receiving the write command;conveying, to the memory device, a column address that identifies a column location of an activated row of the memory core in which to store the write data;conveying, to the memory device, a bank address that identifies a bank of the memory core that contains the column location; andconveying the write data to the memory device after a second delay time has transpired from when the write command was conveyed to the memory device.

26. The method of claim 25, wherein the sense command is included in a first control packet and the write command is included in a second control packet.

27. The method of claim 26, wherein the row address and the bank address that identifies the bank of the memory core that contains the row are included in the first packet, and wherein the column address and the bank address that identifies the bank of the memory core that contains the column location are included in the second packet.

28. The method of claim 25, further comprising: conveying, to the memory device, a read command that specifies that the memory device output data; andreceiving data from the memory device after a third delay time transpires from when the read command was conveyed to the memory device, wherein the second delay time is based on the third delay such that the second delay time is a channel turnaround time less than the third delay time.