Robert L. Pitts

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuits and processes for protection of standard cell p...
- Patent number 11,024,620
- Issue date Jun 1, 2021
- Texas Instruments Incorporated
- Thomas J. Aton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits and processes for protection of standard cell p...
- Patent number 10,192,859
- Issue date Jan 29, 2019
- Texas Instruments Incorporated
- Thomas J. Aton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo retention till access mode enabled memory
- Patent number 9,001,570
- Issue date Apr 7, 2015
- Texas Instruments Incorporated
- Rashmi Sachan
- G11 - INFORMATION STORAGE
Information Patent Grant
Marker layer to facilitate mask build with interactive layers
- Patent number 8,595,656
- Issue date Nov 26, 2013
- Texas Instruments Incorporated
- Thomas J. Aton
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Integrated circuit inductor with integrated vias
- Patent number 8,344,479
- Issue date Jan 1, 2013
- Texas Instruments Incorporated
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact fuse which does not touch a metal layer
- Patent number 8,093,716
- Issue date Jan 10, 2012
- Texas Instruments Incorporated
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory power management systems and methods
- Patent number 7,961,546
- Issue date Jun 14, 2011
- Texas Instruments Incorporated
- Hugh T. Mair
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit inductor with integrated vias
- Patent number 7,888,227
- Issue date Feb 15, 2011
- Texas Instruments Incorporated
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Logic block, a multi-track standard cell library, a method of desig...
- Patent number 7,800,409
- Issue date Sep 21, 2010
- Texas Instruments Incorporated
- Robert L. Pitts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating a mask layout and constructing an integrated...
- Patent number 7,784,015
- Issue date Aug 24, 2010
- Texas Instruments Incorporated
- Robert L. Pitts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tunable voltage controller for a sub-circuit and method of operatin...
- Patent number 7,671,663
- Issue date Mar 2, 2010
- Texas Instruments Incorporated
- Theodore W. Houston
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated circuit inductor with integrated vias
- Patent number 7,400,025
- Issue date Jul 15, 2008
- Texas Instruments Incorporated
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for determining transistor degradation mechanisms
- Patent number 6,933,731
- Issue date Aug 23, 2005
- Texas Instruments Incorporated
- Vijay Kumar Reddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with programmable fuse array
- Patent number 6,876,594
- Issue date Apr 5, 2005
- Texas Instruments Incorporated
- Roger C. Griesmer
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive algorithm for electrical fuse programming
- Patent number 6,747,481
- Issue date Jun 8, 2004
- Texas Instruments Incorporated
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for pulling electrically isolated memory cells in...
- Patent number 6,735,146
- Issue date May 11, 2004
- Texas Instruments Incorporated
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for configuring integrated systems on a chip
- Patent number 6,614,703
- Issue date Sep 2, 2003
- Texas Instruments Incorporated
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for storing data in an integrated circuit
- Patent number 6,608,792
- Issue date Aug 19, 2003
- Texas Instruments Incorporated
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit redundancy control
- Patent number 6,567,323
- Issue date May 20, 2003
- Texas Instruments Incorporated
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst access memory system
- Patent number 6,449,193
- Issue date Sep 10, 2002
- Texas Instruments Incorporated
- Andrew Love
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for validating flash memory
- Patent number 6,381,175
- Issue date Apr 30, 2002
- Texas Instruments Incorporated
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Grant
Read/write protected electrical fuse
- Patent number 6,292,422
- Issue date Sep 18, 2001
- Texas Instruments Incorporated
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Grant
Balanced sensing arrangement for flash EEPROM
- Patent number 6,052,308
- Issue date Apr 18, 2000
- Texas Instruments Incorporated
- Robert L. Pitts
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL P...
- Publication number 20180342494
- Publication date Nov 29, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Thomas J. Aton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT CHIP FABRICATION LEADFRAME
- Publication number 20170018483
- Publication date Jan 19, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO RETENTION TILL ACCESS MODE ENABLED MEMORY
- Publication number 20150092475
- Publication date Apr 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Rashmi Sachan
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL P...
- Publication number 20120286331
- Publication date Nov 15, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Thomas J. Aton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS
- Publication number 20120102441
- Publication date Apr 26, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Thomas J. Aton
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
MEMORY POWER MANAGEMENT SYSTEMS AND METHODS
- Publication number 20110216619
- Publication date Sep 8, 2011
- Hugh T. Mair
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS
- Publication number 20110133880
- Publication date Jun 9, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory Power Management Systems and Methods
- Publication number 20100103760
- Publication date Apr 29, 2010
- Hugh T. Mair
- G11 - INFORMATION STORAGE
Information Patent Application
Scribe Seal Structure for Improved Noise Isolation
- Publication number 20090160029
- Publication date Jun 25, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOGIC BLOCK, A MULTI-TRACK STANDARD CELL LIBRARY, A METHOD OF DESIG...
- Publication number 20090033368
- Publication date Feb 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Robert L. Pitts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS
- Publication number 20080286933
- Publication date Nov 20, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TUNABLE VOLTAGE CONTROLLER FOR A SUB-CIRCUIT AND METHOD OF OPERATIN...
- Publication number 20080136497
- Publication date Jun 12, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Theodore W. Houston
- G05 - CONTROLLING REGULATING
Information Patent Application
CIRCUITRY FOR RELIABILITY TESTING AS A FUNCTION OF SLEW
- Publication number 20080089126
- Publication date Apr 17, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Andrew Marshall
- G01 - MEASURING TESTING
Information Patent Application
Contact fuse which does not touch a metal layer
- Publication number 20070023859
- Publication date Feb 1, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Placement methods for standard cell library
- Publication number 20070011639
- Publication date Jan 11, 2007
- Robert L. Pitts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scribe seal structure for improved noise isolation
- Publication number 20060267154
- Publication date Nov 30, 2006
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal contact fuse element
- Publication number 20050247995
- Publication date Nov 10, 2005
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and system for determining transistor degradation mechanisms
- Publication number 20050086038
- Publication date Apr 21, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Vijay Kumar Reddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit inductor with integrated vias
- Publication number 20040232556
- Publication date Nov 25, 2004
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with programmable fuse array
- Publication number 20040129952
- Publication date Jul 8, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Roger C. Griesmer
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE ALGORITHM FOR ELECTRICAL FUSE PROGRAMMING
- Publication number 20040100302
- Publication date May 27, 2004
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Application
Eliminating defective decoupling capacitors
- Publication number 20040085120
- Publication date May 6, 2004
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR PULLING ELECTRICALLY ISOLATED MEMORY CELLS IN...
- Publication number 20040047175
- Publication date Mar 11, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for minimizing bit stress in a non-volatile memor...
- Publication number 20030095439
- Publication date May 22, 2003
- TEXAS INSTRUMENTS INCORPORATED
- Kemal T. San
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for storing data in an integrated circuit
- Publication number 20020145931
- Publication date Oct 10, 2002
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Application
Burst access memory system
- Publication number 20020122335
- Publication date Sep 5, 2002
- Andrew Love
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuit redundancy control
- Publication number 20020118581
- Publication date Aug 29, 2002
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for validating flash memory
- Publication number 20010048611
- Publication date Dec 6, 2001
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for configuring integrated systems on a chip
- Publication number 20010049174
- Publication date Dec 6, 2001
- Robert L. Pitts
- G11 - INFORMATION STORAGE
Information Patent Application
Secure area communication arrester
- Publication number 20010031631
- Publication date Oct 18, 2001
- Robert L. Pitts
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Robert L. Pitts

Person

Patents Grantslast 30 patents

Integrated circuits and processes for protection of standard cell p...

Integrated circuits and processes for protection of standard cell p...

Pseudo retention till access mode enabled memory

Marker layer to facilitate mask build with interactive layers

Integrated circuit inductor with integrated vias

Contact fuse which does not touch a metal layer

Memory power management systems and methods

Integrated circuit inductor with integrated vias

Logic block, a multi-track standard cell library, a method of desig...

Method for generating a mask layout and constructing an integrated...

Tunable voltage controller for a sub-circuit and method of operatin...

Integrated circuit inductor with integrated vias

Method and system for determining transistor degradation mechanisms

Integrated circuit with programmable fuse array

Adaptive algorithm for electrical fuse programming

System and method for pulling electrically isolated memory cells in...

Method and system for configuring integrated systems on a chip

Method and apparatus for storing data in an integrated circuit

Memory circuit redundancy control

Burst access memory system

Method and system for validating flash memory

Read/write protected electrical fuse

Balanced sensing arrangement for flash EEPROM

Patents Applicationslast 30 patents

INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL P...

INTEGRATED CIRCUIT CHIP FABRICATION LEADFRAME

PSEUDO RETENTION TILL ACCESS MODE ENABLED MEMORY

INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL P...

MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS

MEMORY POWER MANAGEMENT SYSTEMS AND METHODS

INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS

Memory Power Management Systems and Methods

Scribe Seal Structure for Improved Noise Isolation

LOGIC BLOCK, A MULTI-TRACK STANDARD CELL LIBRARY, A METHOD OF DESIG...

INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS

TUNABLE VOLTAGE CONTROLLER FOR A SUB-CIRCUIT AND METHOD OF OPERATIN...

CIRCUITRY FOR RELIABILITY TESTING AS A FUNCTION OF SLEW

Contact fuse which does not touch a metal layer

Placement methods for standard cell library

Scribe seal structure for improved noise isolation

Metal contact fuse element

Method and system for determining transistor degradation mechanisms

Integrated circuit inductor with integrated vias

Integrated circuit with programmable fuse array

ADAPTIVE ALGORITHM FOR ELECTRICAL FUSE PROGRAMMING

Eliminating defective decoupling capacitors

SYSTEM AND METHOD FOR PULLING ELECTRICALLY ISOLATED MEMORY CELLS IN...

Method and system for minimizing bit stress in a non-volatile memor...

Method and apparatus for storing data in an integrated circuit

Burst access memory system

Memory circuit redundancy control

Method and system for validating flash memory

Method and system for configuring integrated systems on a chip

Secure area communication arrester