Robert N. Rountree

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Audio system with integral hearing test
- Patent number 10,848,877
- Issue date Nov 24, 2020
- Robert Newton Rountree
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Audio system with integral hearing test
- Patent number 10,375,489
- Issue date Aug 6, 2019
- Robert Newton Rountree
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
JFET ESD protection circuit for low voltage applications
- Patent number 9,035,363
- Issue date May 19, 2015
- Robert Newton Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable SCR for ESD protection
- Patent number 9,029,910
- Issue date May 12, 2015
- Robert N. Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable SCR for ESD protection
- Patent number 8,872,223
- Issue date Oct 28, 2014
- Robert Newton Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
JFET ESD protection circuit for low voltage applications
- Patent number 8,866,200
- Issue date Oct 21, 2014
- Robert Newton Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage efuse programming circuit and method
- Patent number 8,842,488
- Issue date Sep 23, 2014
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Low noise memory array
- Patent number 8,730,711
- Issue date May 20, 2014
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Low noise memory array
- Patent number 8,675,395
- Issue date Mar 18, 2014
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage antifuse programming circuit and method
- Patent number 8,669,806
- Issue date Mar 11, 2014
- Robert Newton Rountree
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage efuse programming circuit and method
- Patent number 8,625,377
- Issue date Jan 7, 2014
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Power supply protection circuit and method
- Patent number 8,525,581
- Issue date Sep 3, 2013
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Low noise memory array
- Patent number 8,482,962
- Issue date Jul 9, 2013
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Low noise memory array
- Patent number 8,477,526
- Issue date Jul 2, 2013
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power, single poly EEPROM cell with voltage divider
- Patent number 8,174,884
- Issue date May 8, 2012
- Texas Instruments Incorporated
- Harvey J. Stiegler
- G11 - INFORMATION STORAGE
Information Patent Grant
Depletion controlled isolation stage
- Patent number 5,977,596
- Issue date Nov 2, 1999
- Texas Instruments Incorporated
- Robert Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Depletion controlled isolation stage
- Patent number 5,925,922
- Issue date Jul 20, 1999
- Texas Instruments Incorporated
- Robert Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Row decoder with level translator
- Patent number 5,808,482
- Issue date Sep 15, 1998
- Texas Instruments Incorporated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Low capacitance bus driver
- Patent number 5,682,110
- Issue date Oct 28, 1997
- Texas Instruments Incorporated
- Robert N. Rountree
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Row decoder with level translator
- Patent number 5,668,485
- Issue date Sep 16, 1997
- Texas Instruments Incorporated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Block specific spare circuit
- Patent number 5,576,633
- Issue date Nov 19, 1996
- Texas Instruments Incorporated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Block specific spare circuit
- Patent number 5,548,225
- Issue date Aug 20, 1996
- Texas Instruments Incorportated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier having shared dummy cell
- Patent number 5,424,977
- Issue date Jun 13, 1995
- Texas Instruments Incorporated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed parallel test architecture
- Patent number 5,394,370
- Issue date Feb 28, 1995
- Texas Instruments Incorporated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed parallel test architecture
- Patent number 5,305,266
- Issue date Apr 19, 1994
- Texas Instruments Incorporated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared dummy cell
- Patent number 5,291,437
- Issue date Mar 1, 1994
- Texas Instruments Incorporated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Output buffer with enhanced electrostatic discharge protection
- Patent number 5,060,037
- Issue date Oct 22, 1991
- Texas Instruments Incorporated
- Robert N. Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cross point array memory device
- Patent number 5,034,920
- Issue date Jul 23, 1991
- Texas Instruments Incorporated
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit structure with enhanced electrostatic discharge protection
- Patent number 4,939,616
- Issue date Jul 3, 1990
- Texas Instruments Incorporated
- Robert N. Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Output buffer with improved ESD protection
- Patent number 4,855,620
- Issue date Aug 8, 1989
- Texas Instruments Incorporated
- Charvaka Duvvury
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
AUDIO SYSTEM WITH INTEGRAL HEARING TEST
- Publication number 20190306636
- Publication date Oct 3, 2019
- Robert Newton Rountree
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
AUDIO SYSTEM WITH INTEGRAL HEARING TEST
- Publication number 20180270590
- Publication date Sep 20, 2018
- Robert Newton Rountree
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMABLE SCR FOR ESD PROTECTION
- Publication number 20150021659
- Publication date Jan 22, 2015
- Robert N. Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS
- Publication number 20140339608
- Publication date Nov 20, 2014
- Robert Newton Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD
- Publication number 20140071774
- Publication date Mar 13, 2014
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Application
LOW NOISE MEMORY ARRAY
- Publication number 20130285192
- Publication date Oct 31, 2013
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Application
LOW NOISE MEMORY ARRAY
- Publication number 20130286716
- Publication date Oct 31, 2013
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Application
LOW VOLTAGE ANTIFUSE PROGRAMMING CIRCUIT AND METHOD
- Publication number 20130229222
- Publication date Sep 5, 2013
- Robert Newton Rountree
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS
- Publication number 20130214333
- Publication date Aug 22, 2013
- Robert Newton Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD
- Publication number 20130201772
- Publication date Aug 8, 2013
- Robert Newton Rountree
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE SCR FOR ESD PROTECTION
- Publication number 20130200428
- Publication date Aug 8, 2013
- Robert Newton Rountree
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER SUPPLY PROTECTION CIRCUIT AND METHOD
- Publication number 20130120056
- Publication date May 16, 2013
- Robert N. Rountree
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW NOISE MEMORY ARRAY
- Publication number 20120275217
- Publication date Nov 1, 2012
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Application
LOW NOISE MEMORY ARRAY
- Publication number 20120275216
- Publication date Nov 1, 2012
- Robert N. Rountree
- G11 - INFORMATION STORAGE
Information Patent Application
Low power, single poly EEPROM cell with voltage divider
- Publication number 20120020162
- Publication date Jan 26, 2012
- Harvey J. Stiegler
- G11 - INFORMATION STORAGE
Information Patent Application
Jeet memory cell
- Publication number 20100097853
- Publication date Apr 22, 2010
- Robert N. Rountree
- G11 - INFORMATION STORAGE

Robert N. Rountree

Person

Patents Grantslast 30 patents

Audio system with integral hearing test

Audio system with integral hearing test

JFET ESD protection circuit for low voltage applications

Programmable SCR for ESD protection

Programmable SCR for ESD protection

JFET ESD protection circuit for low voltage applications

Low voltage efuse programming circuit and method

Low noise memory array

Low noise memory array

Low voltage antifuse programming circuit and method

Low voltage efuse programming circuit and method

Power supply protection circuit and method

Low noise memory array

Low noise memory array

Low power, single poly EEPROM cell with voltage divider

Depletion controlled isolation stage

Depletion controlled isolation stage

Row decoder with level translator

Low capacitance bus driver

Row decoder with level translator

Block specific spare circuit

Block specific spare circuit

Sense amplifier having shared dummy cell

High speed parallel test architecture

High speed parallel test architecture

Shared dummy cell

Output buffer with enhanced electrostatic discharge protection

Cross point array memory device

Circuit structure with enhanced electrostatic discharge protection

Output buffer with improved ESD protection

Patents Applicationslast 30 patents

AUDIO SYSTEM WITH INTEGRAL HEARING TEST

AUDIO SYSTEM WITH INTEGRAL HEARING TEST

PROGRAMMABLE SCR FOR ESD PROTECTION

JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS

LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD

LOW NOISE MEMORY ARRAY

LOW NOISE MEMORY ARRAY

LOW VOLTAGE ANTIFUSE PROGRAMMING CIRCUIT AND METHOD

JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS

LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD

PROGRAMMABLE SCR FOR ESD PROTECTION

POWER SUPPLY PROTECTION CIRCUIT AND METHOD

LOW NOISE MEMORY ARRAY

LOW NOISE MEMORY ARRAY

Low power, single poly EEPROM cell with voltage divider

Jeet memory cell