Rohan Mandrekar

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Merged power delivery
- Patent number 12,170,478
- Issue date Dec 17, 2024
- Apple Inc.
- Alexander B. Uan-Zo-li
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Implementing high-speed signaling via dedicated printed circuit-boa...
- Patent number 11,076,493
- Issue date Jul 27, 2021
- International Business Machines Corporation
- Douglas A. Baska
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Trimmable banked capacitor
- Patent number 11,069,665
- Issue date Jul 20, 2021
- Apple Inc.
- Vidhya Ramachandran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implementing high-speed signaling via dedicated printed circuit-boa...
- Patent number 10,034,393
- Issue date Jul 24, 2018
- International Business Machines Corporation
- Douglas A. Baska
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect array pattern with a 3:1 signal-to-ground ratio
- Patent number 9,972,566
- Issue date May 15, 2018
- International Business Machines Corporation
- Zhaoqing Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Coreless multi-layer circuit substrate with minimized pad capacitance
- Patent number 9,773,725
- Issue date Sep 26, 2017
- International Business Machines Corporation
- Kevin Bills
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect array pattern with a 3:1 signal-to-ground ratio
- Patent number 9,646,925
- Issue date May 9, 2017
- International Business Machines Corporation
- Zhaoqing Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Distribution of power vias in a multi-layer circuit board
- Patent number 9,600,619
- Issue date Mar 21, 2017
- International Business Machines Corporation
- Zhaoqing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distribution of power vias in a multi-layer circuit board
- Patent number 9,594,865
- Issue date Mar 14, 2017
- International Business Machines Corporation
- Zhaoqing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect array pattern with a 3:1 signal-to-ground ratio
- Patent number 9,543,241
- Issue date Jan 10, 2017
- International Business Machines Corporation
- Zhaoqing Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packaging for eight-socket one-hop SMP topology
- Patent number 9,456,506
- Issue date Sep 27, 2016
- International Business Machines Corporation
- John L. Colbert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Packaging for eight-socket one-hop SMP topology
- Patent number 9,445,507
- Issue date Sep 13, 2016
- International Business Machines Corporation
- John L. Colbert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Through-hole-vias in multi-layer printed circuit boards
- Patent number 9,277,653
- Issue date Mar 1, 2016
- Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
- Moises Cases
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High speed differential wiring in glass ceramic MCMS
- Patent number 9,232,645
- Issue date Jan 5, 2016
- International Business Machines Corporation
- Jinwoo Choi
- C04 - CEMENTS CONCRETE ARTIFICIAL STONE CERAMICS REFRACTORIES
Information Patent Grant
High speed differential wiring in glass ceramic MCMS
- Patent number 9,232,646
- Issue date Jan 5, 2016
- International Business Machines Corporation
- Jinwoo Choi
- C04 - CEMENTS CONCRETE ARTIFICIAL STONE CERAMICS REFRACTORIES
Information Patent Grant
Associating workflows with code sections in a document control system
- Patent number 9,146,735
- Issue date Sep 29, 2015
- International Business Machines Corporation
- Robert B. Chumbley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coreless multi-layer circuit substrate with minimized pad capacitance
- Patent number 9,060,428
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Kevin Bills
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Corles multi-layer circuit substrate with minimized pad capacitance
- Patent number 8,975,525
- Issue date Mar 10, 2015
- International Business Machines Corporation
- Kevin Bills
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Through-hole-vias in multi-layer printed circuit boards
- Patent number 8,766,107
- Issue date Jul 1, 2014
- International Business Machines Corporation
- Moises Cases
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Through-hole-vias in multi-layer printed circuit boards
- Patent number 8,658,911
- Issue date Feb 25, 2014
- International Business Machines Corporation
- Moises Cases
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Implementing high-speed signaling via dedicated printed circuit-boa...
- Patent number 8,619,432
- Issue date Dec 31, 2013
- International Business Machines Corporation
- Douglas A. Baska
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Testing an optical fiber connection
- Patent number 8,593,621
- Issue date Nov 26, 2013
- International Business Machines Corporation
- Kevin J. Bills
- G01 - MEASURING TESTING
Information Patent Grant
Coreless multi-layer circuit substrate with minimized pad capacitance
- Patent number 8,389,870
- Issue date Mar 5, 2013
- International Business Machines Corporation
- Kevin Bills
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Redundant clock channel for high reliability connectors
- Patent number 8,257,092
- Issue date Sep 4, 2012
- International Business Machines Corporation
- Sungjun Chun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through hole-vias in multi-layer printed circuit boards
- Patent number 8,242,384
- Issue date Aug 14, 2012
- International Business Machines Corporation
- Moises Cases
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Structure and Method of Fabrication for High Performance Integrated...
- Publication number 20240088032
- Publication date Mar 14, 2024
- Apple Inc.
- Vidhya Ramachandran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Merged Power Delivery
- Publication number 20240063715
- Publication date Feb 22, 2024
- Apple Inc.
- Alexander B. Uan-Zo-li
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
TRIMMABLE BANKED CAPACITOR
- Publication number 20200176427
- Publication date Jun 4, 2020
- Apple Inc.
- Vidhya Ramachandran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPLEMENTING HIGH-SPEED SIGNALING VIA DEDICATED PRINTED CIRCUIT-BOA...
- Publication number 20180352662
- Publication date Dec 6, 2018
- International Business Machines Corporation
- Douglas A. Baska
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO
- Publication number 20170048967
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Zhaoqing Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PAD-TO-PAD EMBEDDED CAPACITANCE IN LIEU OF SIGNAL VIA TRANSITIONS I...
- Publication number 20170004923
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Zhaoqing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAD-TO-PAD EMBEDDED CAPACITANCE IN LIEU OF SIGNAL VIA TRANSITIONS I...
- Publication number 20170006709
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Zhaoqing Chen
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
DISTRIBUTION OF POWER VIAS IN A MULTI-LAYER CIRCUIT BOARD
- Publication number 20160342723
- Publication date Nov 24, 2016
- International Business Machines Corporation
- Zhaoqing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTION OF POWER VIAS IN A MULTI-LAYER CIRCUIT BOARD
- Publication number 20160342724
- Publication date Nov 24, 2016
- International Business Machines Corporation
- Zhaoqing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE
- Publication number 20160225705
- Publication date Aug 4, 2016
- International Business Machines Corporation
- Kevin Bills
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO
- Publication number 20160150638
- Publication date May 26, 2016
- International Business Machines Corporation
- Zhaoqing Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO
- Publication number 20160149611
- Publication date May 26, 2016
- International Business Machines Corporation
- Zhaoqing Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Packaging for Eight-Socket One-Hop SMP Topology
- Publication number 20150271926
- Publication date Sep 24, 2015
- International Business Machines Corporation
- John L. Colbert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Packaging for Eight-Socket One-Hop SMP Topology
- Publication number 20150177794
- Publication date Jun 25, 2015
- International Business Machines Corporation
- John L. Colbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROUGH-MESH-PLANE VIAS IN A MULTI-LAYERED PACKAGE
- Publication number 20150170996
- Publication date Jun 18, 2015
- International Business Machines Corporation
- Dulce M. Altabella Lazzi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH SPEED DIFFERENTIAL WIRING IN GLASS CERAMIC MCMS
- Publication number 20150144382
- Publication date May 28, 2015
- International Business Machines Corporation
- Jinwoo Choi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
HIGH SPEED DIFFERENTIAL WIRING IN GLASS CERAMIC MCMS
- Publication number 20150144252
- Publication date May 28, 2015
- International Business Machines Corporation
- Jinwoo Choi
- C04 - CEMENTS CONCRETE ARTIFICIAL STONE CERAMICS REFRACTORIES
Information Patent Application
THROUGH-HOLE-VIAS IN MULTI-LAYER PRINTED CIRCUIT BOARDS
- Publication number 20140123489
- Publication date May 8, 2014
- International Business Machines Corporation
- MOISES CASES
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
IMPLEMENTING HIGH-SPEED SIGNALING VIA DEDICATED PRINTED CIRCUIT-BOA...
- Publication number 20140075749
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Douglas A. Baska
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CORLES MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE
- Publication number 20130008696
- Publication date Jan 10, 2013
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- Kevin Bills
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE
- Publication number 20130003335
- Publication date Jan 3, 2013
- International Business Machines Corporation
- Kevin Bills
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Through-Hole-Vias In Multi-Layer Printed Circuit Boards
- Publication number 20120200346
- Publication date Aug 9, 2012
- International Business Machines Corporation
- Moises Cases
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Through-Hole-Vias In Multi-Layer Printed Circuit Boards
- Publication number 20120193135
- Publication date Aug 2, 2012
- International Business Machines Corporation
- Moises Cases
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT PACKAGING INCLUDING AUXILIARY CIRCUITRY
- Publication number 20120175763
- Publication date Jul 12, 2012
- International Business Machines Corporation
- PAUL M. HARVEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUNDANT CLOCK CHANNEL FOR HIGH RELIABILITY CONNECTORS
- Publication number 20120120577
- Publication date May 17, 2012
- International Business Machines Corporation
- Sungjun Chun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING HIGH-SPEED SIGNALING VIA DEDICATED PRINTED CIRCUIT-BOA...
- Publication number 20120081873
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Douglas A. Baska
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Testing An Optical Fiber Connection
- Publication number 20110267602
- Publication date Nov 3, 2011
- International Business Machines Corporation
- Kevin J. Bills
- G01 - MEASURING TESTING
Information Patent Application
CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE
- Publication number 20110222224
- Publication date Sep 15, 2011
- International Business Machines Corporation
- Kevin Bills
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Through-Hole-Vias In Multi-Layer Printed Circuit Boards
- Publication number 20110073359
- Publication date Mar 31, 2011
- International Business Machines Corporation
- Moises Cases
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Associating Workflows With Code Sections In A Document Control System
- Publication number 20110023007
- Publication date Jan 27, 2011
- IBM Corporation
- Robert B. Chumbley
- G06 - COMPUTING CALCULATING COUNTING

Rohan Mandrekar

Person

Patents Grantslast 30 patents

Merged power delivery

Implementing high-speed signaling via dedicated printed circuit-boa...

Trimmable banked capacitor

Implementing high-speed signaling via dedicated printed circuit-boa...

Interconnect array pattern with a 3:1 signal-to-ground ratio

Coreless multi-layer circuit substrate with minimized pad capacitance

Interconnect array pattern with a 3:1 signal-to-ground ratio

Distribution of power vias in a multi-layer circuit board

Distribution of power vias in a multi-layer circuit board

Interconnect array pattern with a 3:1 signal-to-ground ratio

Packaging for eight-socket one-hop SMP topology

Packaging for eight-socket one-hop SMP topology

Through-hole-vias in multi-layer printed circuit boards

High speed differential wiring in glass ceramic MCMS

High speed differential wiring in glass ceramic MCMS

Associating workflows with code sections in a document control system

Coreless multi-layer circuit substrate with minimized pad capacitance

Corles multi-layer circuit substrate with minimized pad capacitance

Through-hole-vias in multi-layer printed circuit boards

Through-hole-vias in multi-layer printed circuit boards

Implementing high-speed signaling via dedicated printed circuit-boa...

Testing an optical fiber connection

Coreless multi-layer circuit substrate with minimized pad capacitance

Redundant clock channel for high reliability connectors

Through hole-vias in multi-layer printed circuit boards

Patents Applicationslast 30 patents

Structure and Method of Fabrication for High Performance Integrated...

Merged Power Delivery

TRIMMABLE BANKED CAPACITOR

IMPLEMENTING HIGH-SPEED SIGNALING VIA DEDICATED PRINTED CIRCUIT-BOA...

INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO

PAD-TO-PAD EMBEDDED CAPACITANCE IN LIEU OF SIGNAL VIA TRANSITIONS I...

PAD-TO-PAD EMBEDDED CAPACITANCE IN LIEU OF SIGNAL VIA TRANSITIONS I...

DISTRIBUTION OF POWER VIAS IN A MULTI-LAYER CIRCUIT BOARD

DISTRIBUTION OF POWER VIAS IN A MULTI-LAYER CIRCUIT BOARD

CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE

INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO

INTERCONNECT ARRAY PATTERN WITH A 3:1 SIGNAL-TO-GROUND RATIO

Packaging for Eight-Socket One-Hop SMP Topology

Packaging for Eight-Socket One-Hop SMP Topology

THROUGH-MESH-PLANE VIAS IN A MULTI-LAYERED PACKAGE

HIGH SPEED DIFFERENTIAL WIRING IN GLASS CERAMIC MCMS

HIGH SPEED DIFFERENTIAL WIRING IN GLASS CERAMIC MCMS

THROUGH-HOLE-VIAS IN MULTI-LAYER PRINTED CIRCUIT BOARDS

IMPLEMENTING HIGH-SPEED SIGNALING VIA DEDICATED PRINTED CIRCUIT-BOA...

CORLES MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE

CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE

Through-Hole-Vias In Multi-Layer Printed Circuit Boards

Through-Hole-Vias In Multi-Layer Printed Circuit Boards

INTEGRATED CIRCUIT PACKAGING INCLUDING AUXILIARY CIRCUITRY

REDUNDANT CLOCK CHANNEL FOR HIGH RELIABILITY CONNECTORS

IMPLEMENTING HIGH-SPEED SIGNALING VIA DEDICATED PRINTED CIRCUIT-BOA...

Testing An Optical Fiber Connection

CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE

Through-Hole-Vias In Multi-Layer Printed Circuit Boards

Associating Workflows With Code Sections In A Document Control System