Patent Application
20240088032
Embodiments described herein relate to semiconductor packaging, and more specifically a module with an integrated passive device.
Microelectronic modules commonly include capacitors for a variety of reasons such as smoothing, filtering, bypassing, energy supply, etc. For example, a capacitor can be mounted onto a module substrate alongside another chip, such as a system-on-chip (SOC). Arranging these capacitors outside of the SOC can increase available area for the SOC since the capacitors are separate from the active SOC. This can lead to a lower power density (since larger capacitor can be realized), and increased efficiency. Additionally, since the capacitors are not required to be formed in the same substrate as the active SOC, processing sequences and substrate doping is not tied to SOC logic processing.
Multilayer ceramic capacitors (MLCCs) are the most commonly adopted technology for capacitor fabrication. MLCCs offer relatively high capacitance with low equivalent series inductance. More recently deep trench capacitors have been employed that utilize semiconductor fabrication processes. Such capacitors may have low profile and higher volume capacitance density than the MLCCs.
Microelectronic modules and methods of formation are described. In an embodiment, a microelectronic module includes a module substrate. a chip mounted onto the module substrate, and a semiconductor-based integrated passive device (IPD) between the chip and the module substrate. The semiconductor-based IPD may include a lower back-end-of-the-line (BEOL) stack-up, an upper redistribution layer (RDL) stack-up and a barrier layer therebetween, for example to provide protection against moisture ingress when the upper RDL stack-up includes organic interlayer dielectric (ILD) layers, which can also be implemented in order to create thicker metallization layers with higher metal density and provide lower effective series resistance (ESR) for the semiconductor-based IPD. A variety of additional variations are also described including structures in which the semiconductor-based IPD and chip are hybrid bonded, and in which the semiconductor-based IPD includes ILD layers formed of higher thermal conductivity materials. While several of these features are described and illustrated separately, it is to be appreciated that the various features may also be combined in some embodiments.
Embodiments describe microelectronic modules including a chip and a semiconductor-based integrated passive device (IPD). In particular, the semiconductor-based IPD can be located between the chip and a module substrate rather than laterally adjacent to the chip on the module substrate.
In one aspect location of the semiconductor-based IPD directly underneath a chip can shorten circuit distance and reduce overall inductance. This may be useful for logic chips such as system-on-chip (SOC) including any of a central processing unit (CPU), graphics processing unit (GPU), compute Engine, etc. and combinations thereof that may operate at high power and high frequency. The semiconductor-based IPDs in accordance with embodiments can include capacitors, such as deep trench capacitors, that are fabricated using semiconductor processes and materials. This can allow for very fine features and thin films which can result in ultra-low inductance. It has been observed that such thin films and fine features can also result in higher equivalent series resistance (ESR). In accordance with embodiments, the semiconductor-based IPD can be fabricated using a lower back-end-of-the-line (BEOL) stack-up and an upper RDL stack-up that has thicker wiring layers and higher metal density than the lower BEOL stack-up to provide lower overall equivalent series inductance (ESL) and lower ESR. Notably, the lower BEOL stack-up can be fabricated in a silicon process line, with the upper RDL stack-up can be fabricated in a packaging process line where equipment is not limited to fine feature size and layer thickness. For example, dielectric layers in the lower BEOL stack-up may be deposited using vapor deposition technologies, which can be limited in thicknesses for time constraints. The dielectric layers in the upper RDL stack-up can be deposited using other suitable techniques, such as solution-based techniques that can achieve thicker layers, which leads to thicker metal layers for wiring.
The semiconductor-based IPDs in accordance with embodiments may additionally include through silicon vias (TSVs) to provide connection to the underlying module substrate. The TSVs may be further electrically connected to the upper RDL stack-up. In an exemplary semiconductor-based IPD capacitor structure, the capacitors can be banked (divided into an array of smaller capacitors), with the wiring layers in the upper RDL stack-up providing full power and ground planes. The TSVs can pass through the semiconductor-based IPD and connect the back side of the semiconductor-based IPD to the wiring layer(s) of the upper RDL stack-up which can be fabricated based on a package-like technology with ability to support thick metal and high metal density designs for minimizing resistance.
In accordance with embodiments the semiconductor-based IPDs include the additional upper RDL stack-up and TSVs to provide a component whose ESL and ESR are both low.
Additionally, the BEOL stack-ups allow the formation of a custom bump map, while allowing for a simple underlying IPD design. This can facilitate assembly of the IPD directly to a chip which may have a pre-defined and random bump map. In the case of reconfiguration of the chip bump map, the IPD can be updated by a simply design change in the upper RDL stack-up only, keeping the underlying IPD unchanged. Also, the same basic IPD can be reused multiple times in a design by dimply modifying the upper RDL stack-up. All of the features, make use and reuse of the IPD simple and relatively inexpensive compared to a full custom design that would be needed otherwise.
In another aspect, embodiments describe semiconductor-based IPDs in which hybrid bonding using wafer-on-wafer (WoW) or chip-on-wafer (CoW) techniques can be utilized to form lower impedance metal-mediated high density electrical connections with low profile standoff connectivity. Thermal degradation performance can additionally be improved by forming the upper RDL stack-up of the semiconductor-based IPD with a high thermal conductivity material (compared to silicon oxides and organics) such as silicon nitride (SiN), aluminum nitride (AlN), boron nitride (BN), alumina (Al2O3), and diamond. Such higher thermal conductivity materials may also have higher dielectric constants, which may be acceptable for an IPD where timing can be less important than for a higher performance chip.
In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.
The terms “upper”, “lower”, “over”, “to”, “between”, and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over”, or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
Referring now to
The chip 120 may be mounted onto the module substrate 110 with ball grid array (BGA) solder bumps 122. The semiconductor-based integrated passive device 130 may be bonded to the chip 120 with a first set of (solder) microbumps 132, and bonded to the module substrate 110 with a second set of microbumps 134, both of which may be smaller than solder bumps 122, and my have a smaller pitch than solder bumps 122.
Referring now specifically to
In an embodiment, the lower BEOL stack-up includes one or more lower BEOL wiring layers 142, and the upper RDL stack-up includes one or more upper RDL wiring layers 144. The one or more lower BEOL wiring layers 142 may be formed within one or more lower metallization layers (MA, MB, etc.), and the one or more upper RDL wiring layers 144 may be formed within one or more upper metallization layer (MC, MD, etc.) that are thicker than the lower metallization layers. Thickness of the lower BEOL wiring layers 142 and upper RDL wiring layers 144 may be determined by thickness of the lower BEOL ILD layers 146 and upper RDL IDL layers 148. In an embodiment, the lower BEOL stack-up 136 includes lower oxide ILD layers 146, and the upper RDL stack-up 138 includes upper organic ILD layers 148. The lower ILD layers 146 may include nitrides, traditional oxides (e.g. silicon dioxide) as well as low dielectric constant (low-k) materials, many of which are also oxides. Exemplary low-k lower ILD layers 146 include carbon-doped oxides, fluorine-doped oxides, hydrogen-doped oxides, highly porous oxides such as aerogels and xerogels, and organics. The upper organic ILD layers 148, being formed of organic materials may be more compliant and facilitate metal densities of greater than 60% in the upper RDL wiring layers, or even higher metal densities such as 70% or even 90%. The upper metallization layers (MC, MD, etc.) may additionally include metal planes for power (Vdd) metal planes 149 and ground (Vss) metal planes 141.
By way example, the lower ILD layers 146 may be formed of nitride, oxide and low-k materials, and the lower metallization layers (MA, MB, etc.) may have thickness of less than 1 μm. Lower BEOL wiring layers 142 and vias 143 between lower metallization layers may have a width of less than 1 The upper ILD layers 148 may be formed of organic materials, and upper metallization layers (MC, MD, etc.) may have a thickness of 5 μm or more, such as 5-10 μm. Similarly, upper RDL wiring layers 144 and vias 145 between the upper metallization layers (MC, MD, etc.) may have widths of 5 μm or more, such as 5-10 μm, with Vdd metal planes and Vss metal planes being wider that the upper RDL wiring layers 144.
The semiconductor-based integrated passive device 130 in accordance with embodiments may include a plurality of trench capacitors 150. The trench capacitors 150 may be fabricated using a specific targeted process with optimized capacitors, or a DRAM fabrication process, for example. In an embodiment the semiconductor-based integrated passive device 130 includes a resistive substrate 152 (e.g. silicon substrate, or silicon-on-insulator (SOI) substrate) and the plurality of trench capacitors 150 may be formed within the resistive substrate 152, with the lower BEOL ILD layers 146 including dielectric and metallization layers for interconnection. The trench capacitors 150 in accordance with embodiments may include electrode layers formed of metal or other high conductivity materials. This lowers the equivalent self resistance. Furthermore, the upper RDL wiring layers 144 can interconnect the capacitor cells while keeping equivalent series resistance (ESR) low.
Still referring to
In the particular embodiments illustrated in
Referring now to
It is to be appreciated that the upper RDL stack-up 138 and lower BEOL stack-up 136 may be formed as previously described with regard to
In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming an electronic module with a semiconductor-based integrated passive device. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.
