Rolf Weis

Person

Wappinger Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned buried strap process using doped HDP oxide
- Patent number 6,946,345
- Issue date Sep 20, 2005
- International Business Machines Corporation
- Jochen Beintner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an alignment mark structure using standard proces...
- Patent number 6,825,096
- Issue date Nov 30, 2004
- Infineon Technologies AG
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of fabricating DRAM cells with collar isolation layers
- Patent number 6,797,636
- Issue date Sep 28, 2004
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an alignment mark structure using standard proces...
- Patent number 6,713,884
- Issue date Mar 30, 2004
- Infineon Technologies AG
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned buried strap process using doped HDP oxide
- Patent number 6,667,504
- Issue date Dec 23, 2003
- International Business Machines Corporation
- Jochen Beintner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a single wiring level for transistors with plana...
- Patent number 6,610,573
- Issue date Aug 26, 2003
- Infineon Technologies AG
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of preparing buried LOCOS collar in trench DRAMS
- Patent number 6,599,798
- Issue date Jul 29, 2003
- Infineon Technologies AG
- Helmut Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nitride pattern for improved process window
- Patent number 6,576,944
- Issue date Jun 10, 2003
- Infineon Technologies AG
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process flow for sacrificial collar with polysilicon void
- Patent number 6,544,855
- Issue date Apr 8, 2003
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell configuration
- Patent number 6,496,401
- Issue date Dec 17, 2002
- Infineon Technologies AG
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell with trench capacitor and method of fabricating the mem...
- Patent number 6,420,239
- Issue date Jul 16, 2002
- Infineon Technologies AG
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Self-aligned buried strap process using doped HDP oxide
- Publication number 20040188740
- Publication date Sep 30, 2004
- International Business Machines Corp.
- Jochen Beintner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming an alignment mark structure using standard proces...
- Publication number 20040152270
- Publication date Aug 5, 2004
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of preparing buried LOCOS collar in trench DRAMS
- Publication number 20040115895
- Publication date Jun 17, 2004
- Helmut Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process of fabricating dram cells with collar isolation layers
- Publication number 20030224605
- Publication date Dec 4, 2003
- Infineon Technologies North America Corp.
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming an alignment mark structure using standard proces...
- Publication number 20030119274
- Publication date Jun 26, 2003
- Infineon Technologies North America Corp.
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FLOW FOR SACRIFICIAL COLLAR WITH POLYSILICON VOID
- Publication number 20030077872
- Publication date Apr 24, 2003
- Infineon Technologies North America Corp.
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of preparing buried LOCOS collar in trench DRAMS
- Publication number 20030020112
- Publication date Jan 30, 2003
- Helmut Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PREPARING BURIED LOCOS COLLAR IN TRENCH DRAMS
- Publication number 20030020110
- Publication date Jan 30, 2003
- Helmut Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cell layout with double gate vertical array transistor
- Publication number 20020196651
- Publication date Dec 26, 2002
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a single wiring level for transistors with plana...
- Publication number 20020197801
- Publication date Dec 26, 2002
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned nitride pattern for improved process window
- Publication number 20020076884
- Publication date Jun 20, 2002
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cell configuration
- Publication number 20020005535
- Publication date Jan 17, 2002
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cell with trench capacitor and method of fabricating the mem...
- Publication number 20020004271
- Publication date Jan 10, 2002
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cell with trench, and method for production thereof
- Publication number 20010030337
- Publication date Oct 18, 2001
- Rolf Weis
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Self-aligned buried strap process using doped HDP oxide

Method of forming an alignment mark structure using standard proces...

Process of fabricating DRAM cells with collar isolation layers

Method of forming an alignment mark structure using standard proces...

Self-aligned buried strap process using doped HDP oxide

Method for forming a single wiring level for transistors with plana...

Method of preparing buried LOCOS collar in trench DRAMS

Self-aligned nitride pattern for improved process window

Process flow for sacrificial collar with polysilicon void

Memory cell configuration

Memory cell with trench capacitor and method of fabricating the mem...

Patents Applicationslast 30 patents

Self-aligned buried strap process using doped HDP oxide

Method of forming an alignment mark structure using standard proces...

Method of preparing buried LOCOS collar in trench DRAMS

Process of fabricating dram cells with collar isolation layers

Method of forming an alignment mark structure using standard proces...

PROCESS FLOW FOR SACRIFICIAL COLLAR WITH POLYSILICON VOID

Method of preparing buried LOCOS collar in trench DRAMS

METHOD OF PREPARING BURIED LOCOS COLLAR IN TRENCH DRAMS

Memory cell layout with double gate vertical array transistor

Method for forming a single wiring level for transistors with plana...

Self-aligned nitride pattern for improved process window

Memory cell configuration

Memory cell with trench capacitor and method of fabricating the mem...

Memory cell with trench, and method for production thereof