Ryan Rakvic

Person

Annapolis, MD, US

People

Patents Grantslast 30 patents

Information Patent Grant
Mechanism for monitoring instruction set based thread execution on...
- Patent number 8,887,174
- Issue date Nov 11, 2014
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load balancing for multi-threaded applications via asymmetric power...
- Patent number 8,839,258
- Issue date Sep 16, 2014
- Intel Corporation
- Ryan Rakvic
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Compiler-based scheduling optimization hints for user-level threads
- Patent number 8,205,200
- Issue date Jun 19, 2012
- Intel Corporation
- Shih-wei Liao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load balancing for multi-threaded applications via asymmetric power...
- Patent number 8,108,863
- Issue date Jan 31, 2012
- Intel Corporation
- Ryan Rakvic
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Mechanism for monitoring instruction set based thread execution on...
- Patent number 8,010,969
- Issue date Aug 30, 2011
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequencer address management
- Patent number 7,743,233
- Issue date Jun 22, 2010
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Meeting point thread characterization
- Patent number 7,665,000
- Issue date Feb 16, 2010
- Intel Corporation
- Antonio Gonzalez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel cachelets
- Patent number 7,424,576
- Issue date Sep 9, 2008
- Intel Corporation
- Ryan N. Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicate register file write by an instruction with a pending inst...
- Patent number 7,228,402
- Issue date Jun 5, 2007
- Intel Corporation
- Bohuslav Rychlik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel cachelets
- Patent number 7,216,201
- Issue date May 8, 2007
- Intel Corporation
- Ryan N. Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache mechanism
- Patent number 7,120,749
- Issue date Oct 10, 2006
- Intel Corporation
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Marking in history table instructions slowable/delayable for subseq...
- Patent number 6,954,848
- Issue date Oct 11, 2005
- Intel Corporation
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-vital loads
- Patent number 6,668,306
- Issue date Dec 23, 2003
- Intel Corporation
- Ryan N. Rakvic
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOAD BALANCING FOR MULTI-THREADED APPLICATIONS VIA ASYMMETRIC POWER...
- Publication number 20120131366
- Publication date May 24, 2012
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for Monitoring Instruction Set Based Thread Execution on...
- Publication number 20120017221
- Publication date Jan 19, 2012
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Meeting point thread characterization
- Publication number 20080222466
- Publication date Sep 11, 2008
- Antonio Gonzalez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Load balancing for multi-threaded applications via asymmetric power...
- Publication number 20070157206
- Publication date Jul 5, 2007
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compiler-based scheduling optimization hints for user-level threads
- Publication number 20070124732
- Publication date May 31, 2007
- Shih-wei Lia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling optimizations for user-level threads
- Publication number 20070074217
- Publication date Mar 29, 2007
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for monitoring instruction set based thread execution on...
- Publication number 20060282839
- Publication date Dec 14, 2006
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sequencer address management
- Publication number 20060224858
- Publication date Oct 5, 2006
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel cachelets
- Publication number 20060117141
- Publication date Jun 1, 2006
- Ryan N. Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache mechanism
- Publication number 20050210197
- Publication date Sep 22, 2005
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Predicate register file scoreboarding and renaming
- Publication number 20030135713
- Publication date Jul 17, 2003
- Bohuslav Rychlik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Employing value prediction with the compiler
- Publication number 20030131345
- Publication date Jul 10, 2003
- Chris Wilkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system to identify slowable instructions
- Publication number 20030126412
- Publication date Jul 3, 2003
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASAP instruction caching
- Publication number 20030065906
- Publication date Apr 3, 2003
- Ryan N. Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-vital loads
- Publication number 20020188804
- Publication date Dec 12, 2002
- Ryan N. Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel cachelets
- Publication number 20020188806
- Publication date Dec 12, 2002
- Ryan N. Rakvic
- G06 - COMPUTING CALCULATING COUNTING

Ryan Rakvic

Person

Patents Grantslast 30 patents

Mechanism for monitoring instruction set based thread execution on...

Load balancing for multi-threaded applications via asymmetric power...

Compiler-based scheduling optimization hints for user-level threads

Load balancing for multi-threaded applications via asymmetric power...

Mechanism for monitoring instruction set based thread execution on...

Sequencer address management

Meeting point thread characterization

Parallel cachelets

Predicate register file write by an instruction with a pending inst...

Parallel cachelets

Cache mechanism

Marking in history table instructions slowable/delayable for subseq...

Non-vital loads

Patents Applicationslast 30 patents

LOAD BALANCING FOR MULTI-THREADED APPLICATIONS VIA ASYMMETRIC POWER...

Mechanism for Monitoring Instruction Set Based Thread Execution on...

Meeting point thread characterization

Load balancing for multi-threaded applications via asymmetric power...

Compiler-based scheduling optimization hints for user-level threads

Scheduling optimizations for user-level threads

Mechanism for monitoring instruction set based thread execution on...

Sequencer address management

Parallel cachelets

Cache mechanism

Predicate register file scoreboarding and renaming

Employing value prediction with the compiler

Method and system to identify slowable instructions

ASAP instruction caching

Non-vital loads

Parallel cachelets