Sagar SUTHRAM

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
In-line detection of electrical fails on integrated circuits
- Patent number 12,013,442
- Issue date Jun 18, 2024
- Intel Corporation
- Enlan Yuan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE DO...
- Publication number 20250210587
- Publication date Jun 26, 2025
- Intel Corporation
- Nicolas Butzen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH HIGH CAPA...
- Publication number 20250201768
- Publication date Jun 19, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES FOR HIGH CAPAC...
- Publication number 20250201793
- Publication date Jun 19, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE CO...
- Publication number 20250201766
- Publication date Jun 19, 2025
- Intel Corporation
- Nicolas Butzen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH BOUNDARY...
- Publication number 20250201767
- Publication date Jun 19, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS
- Publication number 20250159953
- Publication date May 15, 2025
- Intel Corporation
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIEN...
- Publication number 20250140741
- Publication date May 1, 2025
- Intel Corporation
- Rajiv Mongia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMORY LAYERS WITH UNIFORM ACCESS
- Publication number 20250107107
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
- Publication number 20250107108
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
- Publication number 20250104760
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY LAYERS AT OPPOSING SIDES OF A COMPLEMENTARY METAL-OXIDE SEMI...
- Publication number 20250098179
- Publication date Mar 20, 2025
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE RE...
- Publication number 20250079398
- Publication date Mar 6, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH A COOLING...
- Publication number 20250079263
- Publication date Mar 6, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AS A SOLID STA...
- Publication number 20250079399
- Publication date Mar 6, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER IN...
- Publication number 20250062278
- Publication date Feb 20, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL FLOATING BODY MEMORY
- Publication number 20250008723
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH CONDUCTIVE LINES EXTENDING OVER SCR...
- Publication number 20240429162
- Publication date Dec 26, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222321
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222326
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR INCLUDING WIDE BAND GAP MATERIALS
- Publication number 20240222438
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR IN A SILICON CARBIDE LAYER AND A TRANSISTOR IN A GALLIUM...
- Publication number 20240222469
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING ROUTING ACROSS LAYERS OF CHANN...
- Publication number 20240222271
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COUPLING A LAYER OF SILICON CARBIDE WITH AN ADJACENT LAYER
- Publication number 20240222435
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL SHARED GATE HIGH-DRIV...
- Publication number 20240222520
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING TWO-LEVEL MEMORY
- Publication number 20240224488
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING LOOKUP TABLE DECODERS FOR FPGAS
- Publication number 20240222276
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222328
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20240222347
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM-ACCESS MEMORY USING WIDE BAND GAP MATERIALS
- Publication number 20240224504
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING BIT-COST SCALING WITH RELAXED...
- Publication number 20240224508
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS

Sagar SUTHRAM

Person

Patents Grantslast 30 patents

In-line detection of electrical fails on integrated circuits

Patents Applicationslast 30 patents

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE DO...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH HIGH CAPA...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES FOR HIGH CAPAC...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE CO...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH BOUNDARY...

INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS

PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIEN...

STACKED MEMORY LAYERS WITH UNIFORM ACCESS

MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION

STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE

MEMORY LAYERS AT OPPOSING SIDES OF A COMPLEMENTARY METAL-OXIDE SEMI...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE RE...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH A COOLING...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AS A SOLID STA...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER IN...

THREE-DIMENSIONAL FLOATING BODY MEMORY

INTEGRATED CIRCUIT DEVICES WITH CONDUCTIVE LINES EXTENDING OVER SCR...

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

TRANSISTOR INCLUDING WIDE BAND GAP MATERIALS

TRANSISTOR IN A SILICON CARBIDE LAYER AND A TRANSISTOR IN A GALLIUM...

INTEGRATED CIRCUIT STRUCTURES HAVING ROUTING ACROSS LAYERS OF CHANN...

COUPLING A LAYER OF SILICON CARBIDE WITH AN ADJACENT LAYER

INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL SHARED GATE HIGH-DRIV...

INTEGRATED CIRCUIT STRUCTURES HAVING TWO-LEVEL MEMORY

INTEGRATED CIRCUIT STRUCTURES HAVING LOOKUP TABLE DECODERS FOR FPGAS

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES

DYNAMIC RANDOM-ACCESS MEMORY USING WIDE BAND GAP MATERIALS

INTEGRATED CIRCUIT STRUCTURES HAVING BIT-COST SCALING WITH RELAXED...