Sailesh Chittipeddi

Person

Lehigh, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Solder bump structure for flip chip semiconductor devices and metho...
- Patent number 8,507,317
- Issue date Aug 13, 2013
- Agere Systems LLC
- Mark A. Bachman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor fabrication method
- Patent number 8,030,199
- Issue date Oct 4, 2011
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder bump structure for flip chip semiconductor devices and metho...
- Patent number 7,952,206
- Issue date May 31, 2011
- Agere Systems Inc.
- Mark A. Bachman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of an integrated circuit structure with reduced dishing i...
- Patent number 7,727,894
- Issue date Jun 1, 2010
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene bond pad structure for lowering stress and allowing...
- Patent number 6,838,769
- Issue date Jan 4, 2005
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonding method for copper interconnects in semiconductor devices
- Patent number 6,790,757
- Issue date Sep 14, 2004
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS vertical replacement gate (VRG) transistors
- Patent number 6,773,994
- Issue date Aug 10, 2004
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing an integrated circuit including a dual-da...
- Patent number 6,762,087
- Issue date Jul 13, 2004
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a semiconductor device
- Patent number 6,706,603
- Issue date Mar 16, 2004
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit die having alignment marks in the bond pad regio...
- Patent number 6,628,001
- Issue date Sep 30, 2003
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for evaluating technology transfer value
- Patent number 6,615,195
- Issue date Sep 2, 2003
- Lucent Technologies Inc.
- Sailesh Chittipeddi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit including ESD circuits for a multi-chip module a...
- Patent number 6,556,409
- Issue date Apr 29, 2003
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench capacitors in SOI substrates
- Patent number 6,552,381
- Issue date Apr 22, 2003
- Agere Systems, INC
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-insulator (SOI) semiconductor structure with additional...
- Patent number 6,538,283
- Issue date Mar 25, 2003
- Lucent Technologies Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for concurrently forming an ESD protection device and a shal...
- Patent number 6,503,793
- Issue date Jan 7, 2003
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing dishing related issues during the formation of...
- Patent number 6,500,729
- Issue date Dec 31, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor fabrication method
- Patent number 6,498,080
- Issue date Dec 24, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device structure including a tantalum pentoxide layer...
- Patent number 6,482,694
- Issue date Nov 19, 2002
- Agere Systems, INC
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonding to copper
- Patent number 6,472,304
- Issue date Oct 29, 2002
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier for copper metallization
- Patent number 6,455,418
- Issue date Sep 24, 2002
- Agere Systems Guardian Corp.
- Siddhartha Bhowmik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolated regions in an integrated circuit
- Patent number 6,445,043
- Issue date Sep 3, 2002
- Agere Systems
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a merged contact window in a transistor to electr...
- Patent number 6,426,263
- Issue date Jul 30, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming a dual damascene bond pad structure over active...
- Patent number 6,417,087
- Issue date Jul 9, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming trench capacitors in SOI substrates
- Patent number 6,387,772
- Issue date May 14, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge protection device with monolithically forme...
- Patent number 6,384,452
- Issue date May 7, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming dual-polysilicon structures using a built-in sto...
- Patent number 6,365,469
- Issue date Apr 2, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing in integrated circuit including a dual-da...
- Patent number 6,365,327
- Issue date Apr 2, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming shallow trench isolation structures
- Patent number 6,358,785
- Issue date Mar 19, 2002
- Lucent Technologies, Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor in an integrated circuit and a method of manufacturing an...
- Patent number 6,348,393
- Issue date Feb 19, 2002
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tungsten formation process
- Patent number 6,323,126
- Issue date Nov 27, 2001
- Agere Systems Guardian Corp.
- Sailesh Chittipeddi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Patents Applicationslast 30 patents

Information Patent Application
CONTACT SUPPORT PILLAR STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICE...
- Publication number 20140015127
- Publication date Jan 16, 2014
- AGERE SYSTEMS LLC
- Mark A. Bachman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHO...
- Publication number 20110195544
- Publication date Aug 11, 2011
- Mark A. Bachman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR FABRICATION METHOD
- Publication number 20100120216
- Publication date May 13, 2010
- Agere Systems Inc.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR FABRICATION METHOD
- Publication number 20080280403
- Publication date Nov 13, 2008
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of an integrated circuit structure with reduced dishing i...
- Publication number 20070228572
- Publication date Oct 4, 2007
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHO...
- Publication number 20070069394
- Publication date Mar 29, 2007
- Agere Systems Inc.
- Mark A. Bachman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wire bonding method for copper interconnects in semiconductor devices
- Publication number 20050035466
- Publication date Feb 17, 2005
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS vertical replacement gate (VRG) transistors
- Publication number 20030119237
- Publication date Jun 26, 2003
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistor fabrication method
- Publication number 20020197838
- Publication date Dec 26, 2002
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a semiconductor device
- Publication number 20020119636
- Publication date Aug 29, 2002
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH CAPACITORS IN SOI SUBSTRSTES
- Publication number 20020094653
- Publication date Jul 18, 2002
- Agere Systems Guardian Crop.
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FORMING A DUAL DAMASCENE BOND PAD STRUCTURE OVER ACTIVE...
- Publication number 20020034871
- Publication date Mar 21, 2002
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING DUAL-POLYSILICON STRUCTURES USING A BUILT- IN ST...
- Publication number 20010046743
- Publication date Nov 29, 2001
- SAILESH CHITTIPEDDI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wire bonding to copper
- Publication number 20010036716
- Publication date Nov 1, 2001
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device structure including a tantalum pentoxide layer...
- Publication number 20010029068
- Publication date Oct 11, 2001
- Sailesh Chittipeddi
- H01 - BASIC ELECTRIC ELEMENTS

Sailesh Chittipeddi

Person

Patents Grantslast 30 patents

Solder bump structure for flip chip semiconductor devices and metho...

Transistor fabrication method

Solder bump structure for flip chip semiconductor devices and metho...

Formation of an integrated circuit structure with reduced dishing i...

Dual damascene bond pad structure for lowering stress and allowing...

Wire bonding method for copper interconnects in semiconductor devices

CMOS vertical replacement gate (VRG) transistors

Process for manufacturing an integrated circuit including a dual-da...

Method of forming a semiconductor device

Integrated circuit die having alignment marks in the bond pad regio...

Method and system for evaluating technology transfer value

Integrated circuit including ESD circuits for a multi-chip module a...

Trench capacitors in SOI substrates

Silicon-on-insulator (SOI) semiconductor structure with additional...

Method for concurrently forming an ESD protection device and a shal...

Method for reducing dishing related issues during the formation of...

Transistor fabrication method

Semiconductor device structure including a tantalum pentoxide layer...

Wire bonding to copper

Barrier for copper metallization

Isolated regions in an integrated circuit

Method for making a merged contact window in a transistor to electr...

Process for forming a dual damascene bond pad structure over active...

Method for forming trench capacitors in SOI substrates

Electrostatic discharge protection device with monolithically forme...

Method for forming dual-polysilicon structures using a built-in sto...

Process for manufacturing in integrated circuit including a dual-da...

Method for forming shallow trench isolation structures

Capacitor in an integrated circuit and a method of manufacturing an...

Tungsten formation process

Patents Applicationslast 30 patents

CONTACT SUPPORT PILLAR STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICE...

SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHO...

TRANSISTOR FABRICATION METHOD

TRANSISTOR FABRICATION METHOD

Formation of an integrated circuit structure with reduced dishing i...

SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHO...

Wire bonding method for copper interconnects in semiconductor devices

CMOS vertical replacement gate (VRG) transistors

Transistor fabrication method

Method of forming a semiconductor device

TRENCH CAPACITORS IN SOI SUBSTRSTES

PROCESS FOR FORMING A DUAL DAMASCENE BOND PAD STRUCTURE OVER ACTIVE...

METHOD FOR FORMING DUAL-POLYSILICON STRUCTURES USING A BUILT- IN ST...

Wire bonding to copper

Semiconductor device structure including a tantalum pentoxide layer...