Claims
- 1. A process for copper metallization of an integrated circuit, comprising the steps of:forming at least one feature on a substrate with an aspect ratio up to about 15:1; forming a tantalum layer between about 5 and 50 nm thick in the feature; forming a tantalum nitride layer between about 5 and 100 nm thick on the tantalum; forming a titanium nitride layer between about 5 and 100 nm thick on the tantalum nitride; and forming a copper layer on the titanium nitride.
- 2. The process of claim 1, wherein the feature in the substrate has an aspect ratio of at least about 2:1.
- 3. The process of claim 2, wherein the feature is selected from the group consisting of windows, trenches and vias.
- 4. The process of claim 1, wherein the thickness of the tantalum nitride is about 10 nm to about 50 nm.
- 5. The process of claim 1, wherein the tantalum, tantalum nitride, and titanium nitride layers are formed by CVD.
- 6. The process of claim 5, wherein the feature on the substrate has an aspect ratio of between about 4.1 and about 15:1.
Parent Case Info
This is a divisional of application Ser. No. 09/218649 now U.S. Pat. No. 6,288,449, filed on Dec. 22, 1998.
US Referenced Citations (21)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2 336 469 |
Oct 1999 |
GB |
Non-Patent Literature Citations (1)
Entry |
“Meeting Report,” Solid State Technology Jul., 1998 Ed Korczynski, Senior Technical Editor. |