Scot A. Kellar

Person

Bend, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Thermal management in horizontally or vertically stacked dies
- Patent number 12,242,315
- Issue date Mar 4, 2025
- Intel Corporation
- Somvir Singh Dahiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit package having rectangular aspect ratio
- Patent number 10,068,866
- Issue date Sep 4, 2018
- Intel Corporation
- Scot A Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor with insulating nanostructure
- Patent number 7,271,434
- Issue date Sep 18, 2007
- Intel Corporation
- Scot A. Kellar
- G11 - INFORMATION STORAGE
Information Patent Grant
Capacitor with conducting nanostructure
- Patent number 7,265,406
- Issue date Sep 4, 2007
- Intel Corporation
- Scot A. Kellar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for on-chip decoupling capacitor using nanostruct...
- Patent number 7,244,983
- Issue date Jul 17, 2007
- Intel Corporation
- Sarah E. Kim
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process of vertically stacking multiple wafers supporting different...
- Patent number 7,157,787
- Issue date Jan 2, 2007
- Intel Corporation
- Sarah E. Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-high capacitance device based on nanostructures
- Patent number 7,091,084
- Issue date Aug 15, 2006
- Intel Corporation
- Scot A. Kellar
- G11 - INFORMATION STORAGE
Information Patent Grant
Barrier structure against corrosion and contamination in three-dime...
- Patent number 7,056,807
- Issue date Jun 6, 2006
- Intel Corporation
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer bonding using a flexible bladder press for three dimensional...
- Patent number 7,037,804
- Issue date May 2, 2006
- Intel Corporation
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer bonding using a flexible bladder press and thinned wafers for...
- Patent number 6,975,016
- Issue date Dec 13, 2005
- Intel Corporation
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-high capacitance device based on nanostructures
- Patent number 6,911,373
- Issue date Jun 28, 2005
- Intel Corporation
- Scot A. Kellar
- G11 - INFORMATION STORAGE
Information Patent Grant
Dielectric recess for wafer-to-wafer and die-to-die metal bonding a...
- Patent number 6,887,769
- Issue date May 3, 2005
- Intel Corporation
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of vertically stacking multiple wafers supporting different...
- Patent number 6,762,076
- Issue date Jul 13, 2004
- Intel Corporation
- Sarah E. Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier structure against corrosion and contamination in three-dime...
- Patent number 6,661,085
- Issue date Dec 9, 2003
- Intel Corporation
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and device for on-chip decoupling capacitor using nanostruct...
- Patent number 6,599,808
- Issue date Jul 29, 2003
- Intel Corporation
- Sarah E. Kim
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
THERMAL MANAGEMENT IN HORIZONTALLY OR VERTICALLY STACKED DIES
- Publication number 20250231601
- Publication date Jul 17, 2025
- Intel Corporation
- Somvir Singh Dahiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO CONTROL TEMPERATURE RAMP RATES INCLUDING TE...
- Publication number 20240329722
- Publication date Oct 3, 2024
- Intel Corporation
- Somvir DAHIYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMAL MANAGEMENT IN HORIZONTALLY OR VERTICALLY STACKED DIES
- Publication number 20220300049
- Publication date Sep 22, 2022
- Intel Corporation
- Somvir Singh Dahiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PACKAGE HAVING RECTANGULAR ASPECT RATIO
- Publication number 20180090462
- Publication date Mar 29, 2018
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process of vertically stacking multiple wafers supporting different...
- Publication number 20070111386
- Publication date May 17, 2007
- Sarah E. Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Capacitor with conducting nanostructure
- Publication number 20050194628
- Publication date Sep 8, 2005
- Scot A. Kellar
- G11 - INFORMATION STORAGE
Information Patent Application
Ultra-high capacitance device based on nanostructures
- Publication number 20050151261
- Publication date Jul 14, 2005
- Scot A. Kellar
- G11 - INFORMATION STORAGE
Information Patent Application
Method and device for on-chip decoupling capacitor using nanostruct...
- Publication number 20050101099
- Publication date May 12, 2005
- Sarah E. Kim
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Process of vertically stacking multiple wafers supporting different...
- Publication number 20040219763
- Publication date Nov 4, 2004
- Sarah E. Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer bonding for three-dimensional (3D) integration
- Publication number 20040142540
- Publication date Jul 22, 2004
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ultra-high capacitance device based on nanostructures
- Publication number 20040131774
- Publication date Jul 8, 2004
- Scot A. Kellar
- G11 - INFORMATION STORAGE
Information Patent Application
Ultra-high capacitance device based on nanostructures
- Publication number 20040058504
- Publication date Mar 25, 2004
- Scot A. Kellar
- G11 - INFORMATION STORAGE
Information Patent Application
Barrier structure against corrosion and contamination in three-dime...
- Publication number 20040014308
- Publication date Jan 22, 2004
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dielectric recess for wafer-to-wafer and die-to-die metal bonding a...
- Publication number 20030157782
- Publication date Aug 21, 2003
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process of vertically stacking multiple wafers supporting different...
- Publication number 20030157748
- Publication date Aug 21, 2003
- Sarah E. Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barrier structure against corrosion and contamination in three-dime...
- Publication number 20030148590
- Publication date Aug 7, 2003
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer bonding for three-dimensional (3D) integration
- Publication number 20030148596
- Publication date Aug 7, 2003
- Scot A. Kellar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and device for on-chip decoupling capacitor using nanostruct...
- Publication number 20030064583
- Publication date Apr 3, 2003
- Sarah E. Kim
- B82 - NANO-TECHNOLOGY

Scot A. Kellar

Person

Patents Grantslast 30 patents

Thermal management in horizontally or vertically stacked dies

Integrated circuit package having rectangular aspect ratio

Capacitor with insulating nanostructure

Capacitor with conducting nanostructure

Method and device for on-chip decoupling capacitor using nanostruct...

Process of vertically stacking multiple wafers supporting different...

Ultra-high capacitance device based on nanostructures

Barrier structure against corrosion and contamination in three-dime...

Wafer bonding using a flexible bladder press for three dimensional...

Wafer bonding using a flexible bladder press and thinned wafers for...

Ultra-high capacitance device based on nanostructures

Dielectric recess for wafer-to-wafer and die-to-die metal bonding a...

Process of vertically stacking multiple wafers supporting different...

Barrier structure against corrosion and contamination in three-dime...

Method and device for on-chip decoupling capacitor using nanostruct...

Patents Applicationslast 30 patents

THERMAL MANAGEMENT IN HORIZONTALLY OR VERTICALLY STACKED DIES

APPARATUS AND METHOD TO CONTROL TEMPERATURE RAMP RATES INCLUDING TE...

THERMAL MANAGEMENT IN HORIZONTALLY OR VERTICALLY STACKED DIES

INTEGRATED CIRCUIT PACKAGE HAVING RECTANGULAR ASPECT RATIO

Process of vertically stacking multiple wafers supporting different...

Capacitor with conducting nanostructure

Ultra-high capacitance device based on nanostructures

Method and device for on-chip decoupling capacitor using nanostruct...

Process of vertically stacking multiple wafers supporting different...

Wafer bonding for three-dimensional (3D) integration

Ultra-high capacitance device based on nanostructures

Ultra-high capacitance device based on nanostructures

Barrier structure against corrosion and contamination in three-dime...

Dielectric recess for wafer-to-wafer and die-to-die metal bonding a...

Process of vertically stacking multiple wafers supporting different...

Barrier structure against corrosion and contamination in three-dime...

Wafer bonding for three-dimensional (3D) integration

Method and device for on-chip decoupling capacitor using nanostruct...