Shailesh Shah

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable low voltage reset apparatus for multi-Vdd chips
- Patent number 7,221,200
- Issue date May 22, 2007
- Cypress Semiconductor Corp.
- Prasad Kotra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip select method through double bonding
- Patent number 7,170,179
- Issue date Jan 30, 2007
- Cypress Semiconductor Corp.
- Shailesh Shah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of protecting flash memory from data corruption during fast...
- Patent number 6,822,899
- Issue date Nov 23, 2004
- Cypress Semiconductor Corporation
- Khaled Boulos
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for generating a pulse signal
- Patent number 6,222,393
- Issue date Apr 24, 2001
- Cypress Semiconductor Corporation
- Shailesh Shah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for generating a pulse signal
- Patent number 5,933,032
- Issue date Aug 3, 1999
- Cypress Semiconductor Corp.
- Shailesh Shah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing skew among input signals within a...
- Patent number 5,903,174
- Issue date May 11, 1999
- Cypress Semiconductor Corp.
- Greg J. Landry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dram with hidden refresh
- Patent number 5,835,401
- Issue date Nov 10, 1998
- Cypress Semiconductor Corporation
- Gary W. Green
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst address generator having two modes of operation employing a l...
- Patent number 5,835,970
- Issue date Nov 10, 1998
- Cypress Semiconductor Corp.
- Greg J. Landry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for matching a clock delay to a delay through...
- Patent number 5,652,732
- Issue date Jul 29, 1997
- Cypress Semiconductor Corp.
- Shailesh Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Output preconditioning circuit with an output level latch and a clamp
- Patent number 5,559,465
- Issue date Sep 24, 1996
- Cypress Semiconductor Corporation
- Shailesh Shah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for writing to memory cells in a minimum numbe...
- Patent number 5,490,115
- Issue date Feb 6, 1996
- Cypress Semiconductor Corp.
- Shailesh Shah
- G11 - INFORMATION STORAGE

Shailesh Shah

Person

Patents Grantslast 30 patents

Programmable low voltage reset apparatus for multi-Vdd chips

Chip select method through double bonding

Method of protecting flash memory from data corruption during fast...

Apparatus and method for generating a pulse signal

Apparatus and method for generating a pulse signal

Method and apparatus for reducing skew among input signals within a...

Dram with hidden refresh

Burst address generator having two modes of operation employing a l...

Apparatus and method for matching a clock delay to a delay through...

Output preconditioning circuit with an output level latch and a clamp

Method and apparatus for writing to memory cells in a minimum numbe...