Sreejit Chakravarty

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods, systems and apparatus for in-field testing for generic dia...
- Patent number 11,335,428
- Issue date May 17, 2022
- Intel Corporation
- Asad Azam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test architecture for die to die interconnect for three dimensional...
- Patent number 11,257,560
- Issue date Feb 22, 2022
- Intel Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Grant
In-field system testing
- Patent number 10,859,627
- Issue date Dec 8, 2020
- Intel Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
In-field system test security
- Patent number 10,491,381
- Issue date Nov 26, 2019
- Intel Corporation
- Neel Shah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data transformations to improve ROM yield and programming time
- Patent number 9,256,505
- Issue date Feb 9, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Sreejit Chakravarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-cost design for register file testability
- Patent number 8,793,549
- Issue date Jul 29, 2014
- LSI Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Grant
Victim port-based design for test area overhead reduction in multip...
- Patent number 8,711,645
- Issue date Apr 29, 2014
- LSI Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan cell designs with serial and parallel loading of test data
- Patent number 8,656,233
- Issue date Feb 18, 2014
- LSI Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
Stored-pattern logic self-testing with serial communication
- Patent number 8,583,973
- Issue date Nov 12, 2013
- LSI Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
Critical path monitor for an integrated circuit and method of opera...
- Patent number 8,499,230
- Issue date Jul 30, 2013
- LSI Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
Timing error sampling generator and a method of timing testing
- Patent number 8,473,890
- Issue date Jun 25, 2013
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic BIST for system testing using stored patterns
- Patent number 8,473,792
- Issue date Jun 25, 2013
- LSI Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
Electronic design automation tool and method for employing unsensit...
- Patent number 8,464,198
- Issue date Jun 11, 2013
- LSI Corporation
- Sreejit Chakravarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test technique to apply a variable scan clock including a scan cloc...
- Patent number 8,418,008
- Issue date Apr 9, 2013
- LSI Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
Low cost comparator design for memory BIST
- Patent number 8,228,750
- Issue date Jul 24, 2012
- LSI Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing error sampling generator, critical path monitor for hold and...
- Patent number 8,191,029
- Issue date May 29, 2012
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing memory power management modes in an i...
- Patent number 8,090,965
- Issue date Jan 3, 2012
- LSI Corporation
- Sreejit Chakravarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic design automation tool and method for optimizing the pla...
- Patent number 8,010,935
- Issue date Aug 30, 2011
- LSI Corporation
- Alexander Tetelbaum
- G01 - MEASURING TESTING
Information Patent Grant
System and method for reducing the generation of inconsequential vi...
- Patent number 7,971,169
- Issue date Jun 28, 2011
- LSI Corporation
- Alexander Y. Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced logic built-in self-test module and method of online syste...
- Patent number 7,802,159
- Issue date Sep 21, 2010
- LSI Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
Scaleable approach to extracting bridges from a hierarchically desc...
- Patent number 6,598,211
- Issue date Jul 22, 2003
- Intel Corporation
- Sujit T. Zachariah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for extracting bridges from an integrated circ...
- Patent number 6,519,499
- Issue date Feb 11, 2003
- Intel Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for extracting bridges from an integrated circ...
- Patent number 6,502,004
- Issue date Dec 31, 2002
- Intel Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TEST AND REPAIR ARCHITECTURE FOR INTER AND INTRA CLUSTER DEFECTS
- Publication number 20250068529
- Publication date Feb 27, 2025
- Intel Corporation
- Sreejit CHAKRAVARTY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST AND REPAIR OF INTERCONNECTS BETWEEN CHIPS
- Publication number 20240027516
- Publication date Jan 25, 2024
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Application
RUNTIME NON-DESTRUCTIVE MEMORY BUILT-IN SELF-TEST (BIST)
- Publication number 20230084463
- Publication date Mar 16, 2023
- Intel Corporation
- Sreejit CHAKRAVARTY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE...
- Publication number 20190096503
- Publication date Mar 28, 2019
- Intel Corporation
- Sreejit CHAKRAVARTY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS, SYSTEMS AND APPARATUS FOR IN-FIELD TESTING FOR GENERIC DIA...
- Publication number 20190051370
- Publication date Feb 14, 2019
- Intel Corporation
- Asad Azam
- G11 - INFORMATION STORAGE
Information Patent Application
In-Field System Testing
- Publication number 20190004112
- Publication date Jan 3, 2019
- Sreejit Chakravarty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
IN-FIELD SYSTEM TEST SECURITY
- Publication number 20190007200
- Publication date Jan 3, 2019
- Intel Corporation
- Neel Shah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR REDUCING MEMORY TEST TIME UTILIZING A BUILT-I...
- Publication number 20150262710
- Publication date Sep 17, 2015
- LSI Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Application
DATA TRANSFORMATIONS TO IMPROVE ROM YIELD AND PROGRAMMING TIME
- Publication number 20150261636
- Publication date Sep 17, 2015
- LSI Corporation
- Sreejit Chakravarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Victim Port-Based Design for Test Area Overhead Reduction in Multip...
- Publication number 20130258786
- Publication date Oct 3, 2013
- LSI Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN TEST CIRCUITRY COMPRISING SCAN CELLS WITH FUNCTIONAL OUTPUT MU...
- Publication number 20130111285
- Publication date May 2, 2013
- LSI Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Application
TIMING ERROR SAMPLING GENERATOR AND A METHOD OF TIMING TESTING
- Publication number 20120278780
- Publication date Nov 1, 2012
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC BIST FOR SYSTEM TESTING USING STORED PATTERNS
- Publication number 20120179946
- Publication date Jul 12, 2012
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Application
SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA
- Publication number 20120173938
- Publication date Jul 5, 2012
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Application
SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA
- Publication number 20120173939
- Publication date Jul 5, 2012
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Application
LOW COST COMPARATOR DESIGN FOR MEMORY BIST
- Publication number 20120063248
- Publication date Mar 15, 2012
- LSI Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Application
LOW-COST DESIGN FOR REGISTER FILE TESTABILITY
- Publication number 20120042220
- Publication date Feb 16, 2012
- LSI Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Application
DFT TECHNIQUE TO APPLY A VARIABLE SCAN CLOCK INCLUDING A SCAN CLOCK...
- Publication number 20100162060
- Publication date Jun 24, 2010
- LSI Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Application
TIMING ERROR SAMPLING GENERATOR, CRITICAL PATH MONITOR FOR HOLD AND...
- Publication number 20100153895
- Publication date Jun 17, 2010
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL PATH MONITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF OPERA...
- Publication number 20090278576
- Publication date Nov 12, 2009
- LSI Corporation
- Sreejit Chakravarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLA...
- Publication number 20090282381
- Publication date Nov 12, 2009
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scaleable approach to extracting bridges from a hierarchically desc...
- Publication number 20020144219
- Publication date Oct 3, 2002
- Sujit T. Zachariah
- G06 - COMPUTING CALCULATING COUNTING

Sreejit Chakravarty

Person

Patents Grantslast 30 patents

Methods, systems and apparatus for in-field testing for generic dia...

Test architecture for die to die interconnect for three dimensional...

In-field system testing

In-field system test security

Data transformations to improve ROM yield and programming time

Low-cost design for register file testability

Victim port-based design for test area overhead reduction in multip...

Scan cell designs with serial and parallel loading of test data

Stored-pattern logic self-testing with serial communication

Critical path monitor for an integrated circuit and method of opera...

Timing error sampling generator and a method of timing testing

Logic BIST for system testing using stored patterns

Electronic design automation tool and method for employing unsensit...

Test technique to apply a variable scan clock including a scan cloc...

Low cost comparator design for memory BIST

Timing error sampling generator, critical path monitor for hold and...

System and method for testing memory power management modes in an i...

Electronic design automation tool and method for optimizing the pla...

System and method for reducing the generation of inconsequential vi...

Enhanced logic built-in self-test module and method of online syste...

Scaleable approach to extracting bridges from a hierarchically desc...

Method and apparatus for extracting bridges from an integrated circ...

Method and apparatus for extracting bridges from an integrated circ...

Patents Applicationslast 30 patents

TEST AND REPAIR ARCHITECTURE FOR INTER AND INTRA CLUSTER DEFECTS

TEST AND REPAIR OF INTERCONNECTS BETWEEN CHIPS

RUNTIME NON-DESTRUCTIVE MEMORY BUILT-IN SELF-TEST (BIST)

DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE...

METHODS, SYSTEMS AND APPARATUS FOR IN-FIELD TESTING FOR GENERIC DIA...

In-Field System Testing

IN-FIELD SYSTEM TEST SECURITY

METHOD AND SYSTEM FOR REDUCING MEMORY TEST TIME UTILIZING A BUILT-I...

DATA TRANSFORMATIONS TO IMPROVE ROM YIELD AND PROGRAMMING TIME

Victim Port-Based Design for Test Area Overhead Reduction in Multip...

SCAN TEST CIRCUITRY COMPRISING SCAN CELLS WITH FUNCTIONAL OUTPUT MU...

TIMING ERROR SAMPLING GENERATOR AND A METHOD OF TIMING TESTING

LOGIC BIST FOR SYSTEM TESTING USING STORED PATTERNS

SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA

SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA

LOW COST COMPARATOR DESIGN FOR MEMORY BIST

LOW-COST DESIGN FOR REGISTER FILE TESTABILITY

DFT TECHNIQUE TO APPLY A VARIABLE SCAN CLOCK INCLUDING A SCAN CLOCK...

TIMING ERROR SAMPLING GENERATOR, CRITICAL PATH MONITOR FOR HOLD AND...

CRITICAL PATH MONITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF OPERA...

ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLA...

Scaleable approach to extracting bridges from a hierarchically desc...