Srisai Rao Seethamraju

Person

Nashua, NH, US

People

Patents Grantslast 30 patents

Information Patent Grant
Jitter self-test using timestamps
- Patent number 11,764,913
- Issue date Sep 19, 2023
- Skyworks Solutions, Inc.
- Raghunandan K. Ranganathan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronizing update of time of day counters using time stamp excha...
- Patent number 11,496,234
- Issue date Nov 8, 2022
- Skyworks Solutions, Inc.
- Srisai Rao Seethamraju
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Correction for period error in a reference clock signal
- Patent number 11,316,522
- Issue date Apr 26, 2022
- Silicon Laboratories Inc.
- Aslamali A. Rafi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for generation of independent clock signals from the same os...
- Patent number 11,245,406
- Issue date Feb 8, 2022
- Silicon Laboratories Inc.
- Harihara Subramanian Ranganathan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Jitter self-test using timestamps
- Patent number 11,228,403
- Issue date Jan 18, 2022
- Skyworks Solutions, Inc.
- Raghunandan K. Ranganathan
- G01 - MEASURING TESTING
Information Patent Grant
Spur and quantization noise cancellation for PLLS with non-linear p...
- Patent number 11,038,521
- Issue date Jun 15, 2021
- Silicon Laboratories Inc.
- Aslamali A. Rafi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Noise canceling technique for a sine to square wave converter
- Patent number 10,840,897
- Issue date Nov 17, 2020
- Silicon Laboratories Inc.
- Aslamali A. Rafi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compensating for thermal lag in temperature compensated crystal osc...
- Patent number 10,404,209
- Issue date Sep 3, 2019
- Silicon Laboratories Inc.
- Joseph D. Cali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compensating for temperature-dependent hysteresis in a temperature...
- Patent number 10,164,643
- Issue date Dec 25, 2018
- Silicon Laboratories Inc.
- Srisai R. Seethamraju
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Amplifier topology achieving high DC gain and wide output voltage r...
- Patent number 9,444,406
- Issue date Sep 13, 2016
- Silicon Laboratories Inc.
- Michael H. Perrott
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Glitchless clock switching that handles stopped clocks
- Patent number 9,207,704
- Issue date Dec 8, 2015
- Silicon Laboratories, Inc.
- William J. Anker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple signal format output driver with configurable internal load
- Patent number 8,823,414
- Issue date Sep 2, 2014
- Silicon Laboratories Inc.
- Rajesh Thirugnanam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital hold in a phase-locked loop
- Patent number 8,532,243
- Issue date Sep 10, 2013
- Silicon Laboratories Inc.
- Srisai R. Seethamraju
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compensation for crystal offset in PLL-based crystal oscillators
- Patent number 8,242,849
- Issue date Aug 14, 2012
- Silicon Laboratories Inc.
- Srisai R. Seethamraju
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase adjustment for a divider circuit
- Patent number 7,459,948
- Issue date Dec 2, 2008
- Silicon Laboratories Inc.
- Srisai Rao Seethamraju
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable phase-locked loop responsive to a selected bandwidth a...
- Patent number 7,443,250
- Issue date Oct 28, 2008
- Silicon Laboratories Inc.
- Srisai R. Seethamraju
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Technique for switching between input clocks in a phase-locked loop
- Patent number 7,405,628
- Issue date Jul 29, 2008
- Silicon Laboratories Inc.
- Ronald B. Hulfachor
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SYNCHRONIZING UPDATE OF TIME OF DAY COUNTERS USING TIME STAMP EXCHA...
- Publication number 20230208543
- Publication date Jun 29, 2023
- Skyworks Solutions, Inc.
- Srisai Rao Seethamraju
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE NOISE PERFORMANCE USING MULTIPLE RESONATORS WITH VARYING QUAL...
- Publication number 20220407526
- Publication date Dec 22, 2022
- Skyworks Solutions, Inc.
- Aslamali A. Rafi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
JITTER SELF-TEST USING TIMESTAMPS
- Publication number 20220123877
- Publication date Apr 21, 2022
- Skyworks Solutions, Inc.
- Raghunandan K. Ranganathan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD FOR GENERATION OF INDEPENDENT CLOCK SIGNALS FROM THE SAME OS...
- Publication number 20210409031
- Publication date Dec 30, 2021
- Silicon Laboratories Inc.
- Harihara Subramanian Ranganathan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CORRECTION FOR PERIOD ERROR IN A REFERENCE CLOCK SIGNAL
- Publication number 20210391864
- Publication date Dec 16, 2021
- Silicon Laboratories Inc.
- Aslamali A. Rafi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
JITTER SELF-TEST USING TIMESTAMPS
- Publication number 20210176020
- Publication date Jun 10, 2021
- Silicon Laboratories Inc.
- Raghunandan K. Ranganathan
- G01 - MEASURING TESTING
Information Patent Application
Synchronizing Update of Time of Day Counters Using Time Stamp Excha...
- Publication number 20190379475
- Publication date Dec 12, 2019
- Silicon Laboratories Inc.
- Srisai Rao Seethamraju
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COMPENSATING FOR TEMPERATURE-DEPENDENT HYSTERESIS IN A TEMPERATURE...
- Publication number 20180076819
- Publication date Mar 15, 2018
- Silicon Laboratories Inc.
- Srisai R. Seethamraju
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMPENSATING FOR THERMAL LAG IN TEMPERATURE COMPENSATED CRYSTAL OSC...
- Publication number 20180069553
- Publication date Mar 8, 2018
- Silicon Laboratories Inc.
- Joseph D. Cali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GLITCHLESS CLOCK SWITCHING THAT HANDLES STOPPED CLOCKS
- Publication number 20140118033
- Publication date May 1, 2014
- Silicon Laboratories Inc.
- William J. Anker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE SIGNAL FORMAT OUTPUT DRIVER WITH CONFIGURABLE INTERNAL LOAD
- Publication number 20130300455
- Publication date Nov 14, 2013
- Rajesh Thirugnanam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL HOLD IN A PHASE-LOCKED LOOP
- Publication number 20080191762
- Publication date Aug 14, 2008
- Srisai R. Seethamraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE PHASE-LOCKED LOOP RESPONSIVE TO A SELECTED BANDWIDTH A...
- Publication number 20080079510
- Publication date Apr 3, 2008
- Srisai R. Seethamraju
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TECHNIQUE FOR SWITCHING BETWEEN INPUT CLOCKS IN A PHASE-LOCKED LOOP
- Publication number 20080079501
- Publication date Apr 3, 2008
- Ronald B. Hulfachor
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase adjustment for a divider circuit
- Publication number 20070001718
- Publication date Jan 4, 2007
- Silicon Laboratories Inc.
- Srisai Rao Seethamraju
- H03 - BASIC ELECTRONIC CIRCUITRY

Srisai Rao Seethamraju

Person

Patents Grantslast 30 patents

Jitter self-test using timestamps

Synchronizing update of time of day counters using time stamp excha...

Correction for period error in a reference clock signal

Method for generation of independent clock signals from the same os...

Jitter self-test using timestamps

Spur and quantization noise cancellation for PLLS with non-linear p...

Noise canceling technique for a sine to square wave converter

Compensating for thermal lag in temperature compensated crystal osc...

Compensating for temperature-dependent hysteresis in a temperature...

Amplifier topology achieving high DC gain and wide output voltage r...

Glitchless clock switching that handles stopped clocks

Multiple signal format output driver with configurable internal load

Digital hold in a phase-locked loop

Compensation for crystal offset in PLL-based crystal oscillators

Phase adjustment for a divider circuit

Programmable phase-locked loop responsive to a selected bandwidth a...

Technique for switching between input clocks in a phase-locked loop

Patents Applicationslast 30 patents

SYNCHRONIZING UPDATE OF TIME OF DAY COUNTERS USING TIME STAMP EXCHA...

PHASE NOISE PERFORMANCE USING MULTIPLE RESONATORS WITH VARYING QUAL...

JITTER SELF-TEST USING TIMESTAMPS

METHOD FOR GENERATION OF INDEPENDENT CLOCK SIGNALS FROM THE SAME OS...

CORRECTION FOR PERIOD ERROR IN A REFERENCE CLOCK SIGNAL

JITTER SELF-TEST USING TIMESTAMPS

Synchronizing Update of Time of Day Counters Using Time Stamp Excha...

COMPENSATING FOR TEMPERATURE-DEPENDENT HYSTERESIS IN A TEMPERATURE...

COMPENSATING FOR THERMAL LAG IN TEMPERATURE COMPENSATED CRYSTAL OSC...

GLITCHLESS CLOCK SWITCHING THAT HANDLES STOPPED CLOCKS

MULTIPLE SIGNAL FORMAT OUTPUT DRIVER WITH CONFIGURABLE INTERNAL LOAD

DIGITAL HOLD IN A PHASE-LOCKED LOOP

PROGRAMMABLE PHASE-LOCKED LOOP RESPONSIVE TO A SELECTED BANDWIDTH A...

TECHNIQUE FOR SWITCHING BETWEEN INPUT CLOCKS IN A PHASE-LOCKED LOOP

Phase adjustment for a divider circuit