Stephen Kornachuk

Person

Campbell, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor chip including a chip level based on a layout that in...
- Patent number 9,754,878
- Issue date Sep 5, 2017
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enforcement of semiconductor structure regularity for localized tra...
- Patent number 9,530,734
- Issue date Dec 27, 2016
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enforcement of semiconductor structure regularity for localized tra...
- Patent number 9,202,779
- Issue date Dec 1, 2015
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enforcement of semiconductor structure regularity for localized tra...
- Patent number 8,701,071
- Issue date Apr 15, 2014
- Tela Innovations, Inc.
- Stephen Kornachuk
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Enforcement of semiconductor structure regularity for localized tra...
- Patent number 8,453,094
- Issue date May 28, 2013
- Tela Innovations, Inc.
- Stephen Kornachuk
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Optimizing layout of irregular structures in regular layout context
- Patent number 8,448,102
- Issue date May 21, 2013
- Tela Innovations, Inc.
- Stephen Kornachuk
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Methods for defining contact grid in dynamic array architecture
- Patent number 8,225,261
- Issue date Jul 17, 2012
- Tela Innovations, Inc.
- Joseph Hong
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory timing apparatus and associated methods
- Patent number 7,586,800
- Issue date Sep 8, 2009
- Tela Innovations, Inc.
- Stephen Kornachuk
- G11 - INFORMATION STORAGE
Information Patent Grant
Speculative sense enable tuning apparatus and associated methods
- Patent number 7,577,049
- Issue date Aug 18, 2009
- Tela Innovations, Inc.
- Stephen Kornachuk
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power differential signal transition techniques for use in memo...
- Patent number 6,072,730
- Issue date Jun 6, 2000
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable universal test interface for testing memories with dif...
- Patent number 6,044,481
- Issue date Mar 28, 2000
- Artisan Components, Inc.
- Steve P. Kornachuk
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed memory self-timing circuitry and methods for implementin...
- Patent number 5,999,482
- Issue date Dec 7, 1999
- Artisan Components, Inc.
- Steve P. Kornachuk
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable universal test interface and method for making the same
- Patent number 5,968,192
- Issue date Oct 19, 1999
- Artisan Components, Inc.
- Steve P. Kornachuk
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit layout methods and layout structures
- Patent number 5,965,925
- Issue date Oct 12, 1999
- Artisan Components, Inc.
- Steve P. Kornachuk
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage sense amplifier and methods for implementing the same
- Patent number 5,889,715
- Issue date Mar 30, 1999
- Artisan Components, Inc.
- Steve P. Kornachuk
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed addressing buffer and methods for implementing same
- Patent number 5,886,929
- Issue date Mar 23, 1999
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed memory output circuitry and methods for implementing same
- Patent number 5,751,649
- Issue date May 12, 1998
- Artisan Components, Inc.
- Steve P. Kornachuk
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Optimizing Layout of Irregular Structures in Regular Layout Context
- Publication number 20170365548
- Publication date Dec 21, 2017
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enforcement of Semiconductor Structure Regularity for Localized Tra...
- Publication number 20170098602
- Publication date Apr 6, 2017
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enforcement of Semiconductor Structure Regularity for Localized Tra...
- Publication number 20160079159
- Publication date Mar 17, 2016
- Tela Innovations, Inc.
- Stephen Kornachuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Enforcement of Semiconductor Structure Regularity for Localized Tra...
- Publication number 20140197543
- Publication date Jul 17, 2014
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing Layout of Irregular Structures in Regular Layout Context
- Publication number 20130256898
- Publication date Oct 3, 2013
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enforcement of Semiconductor Structure Regularity for Localized Tra...
- Publication number 20130254732
- Publication date Sep 26, 2013
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for Consumption of Timing Margin to Reduce Power Utilizatio...
- Publication number 20110156167
- Publication date Jun 30, 2011
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing Layout of Irregular Structures in Regular Layout Context
- Publication number 20090300575
- Publication date Dec 3, 2009
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for Defining Contact Grid in Dynamic Array Architecture
- Publication number 20090228853
- Publication date Sep 10, 2009
- Tela Innovations, Inc.
- Joseph Hong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enforcement of Semiconductor Structure Regularity for Localized Tra...
- Publication number 20090228857
- Publication date Sep 10, 2009
- Tela Innovations, Inc.
- Stephen Kornachuk
- G06 - COMPUTING CALCULATING COUNTING

Stephen Kornachuk

Person

Patents Grantslast 30 patents

Semiconductor chip including a chip level based on a layout that in...

Enforcement of semiconductor structure regularity for localized tra...

Enforcement of semiconductor structure regularity for localized tra...

Enforcement of semiconductor structure regularity for localized tra...

Enforcement of semiconductor structure regularity for localized tra...

Optimizing layout of irregular structures in regular layout context

Methods for defining contact grid in dynamic array architecture

Memory timing apparatus and associated methods

Speculative sense enable tuning apparatus and associated methods

Low power differential signal transition techniques for use in memo...

Programmable universal test interface for testing memories with dif...

High speed memory self-timing circuitry and methods for implementin...

Programmable universal test interface and method for making the same

Integrated circuit layout methods and layout structures

Voltage sense amplifier and methods for implementing the same

High speed addressing buffer and methods for implementing same

High speed memory output circuitry and methods for implementing same

Patents Applicationslast 30 patents

Optimizing Layout of Irregular Structures in Regular Layout Context

Enforcement of Semiconductor Structure Regularity for Localized Tra...

Enforcement of Semiconductor Structure Regularity for Localized Tra...

Enforcement of Semiconductor Structure Regularity for Localized Tra...

Optimizing Layout of Irregular Structures in Regular Layout Context

Enforcement of Semiconductor Structure Regularity for Localized Tra...

Methods for Consumption of Timing Margin to Reduce Power Utilizatio...

Optimizing Layout of Irregular Structures in Regular Layout Context

Methods for Defining Contact Grid in Dynamic Array Architecture

Enforcement of Semiconductor Structure Regularity for Localized Tra...