Stephen M. Douglass

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configurable logic fabric including two fixed logic processors with...
- Patent number 7,539,848
- Issue date May 26, 2009
- Xilinx, Inc.
- Stephen M. Douglass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable gate array and embedded circuitry initialization and p...
- Patent number 7,420,392
- Issue date Sep 2, 2008
- Xilinx, Inc.
- David P. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing of an integrated circuit having an embedded processor
- Patent number 7,406,670
- Issue date Jul 29, 2008
- Xilinx, Inc.
- Ahmad R. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing of an integrated circuit having an embedded processor
- Patent number 7,269,805
- Issue date Sep 11, 2007
- Xilinx, Inc.
- Ahmad R. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speed verification of an embedded processor in a programmable logic...
- Patent number 7,231,621
- Issue date Jun 12, 2007
- Xilinx, Inc.
- Nigel G. Herron
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for processing data with a programmable gate a...
- Patent number 7,194,600
- Issue date Mar 20, 2007
- Xilinx, Inc.
- Stephen M. Douglass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of designing integrated circuit having both configurable and...
- Patent number 6,961,919
- Issue date Nov 1, 2005
- Xilinx, Inc.
- Stephen M. Douglass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Custom code processing in PGA by providing instructions from fixed...
- Patent number 6,886,092
- Issue date Apr 26, 2005
- Xilinx, Inc.
- Stephen M. Douglass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable gate array having interconnecting logic to support emb...
- Patent number 6,798,239
- Issue date Sep 28, 2004
- Xilinx, Inc.
- Stephen M. Douglass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floor planning for programmable gate array having embedded fixed lo...
- Patent number 6,693,452
- Issue date Feb 17, 2004
- Xilinx, Inc.
- Ahmad R. Ansari
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
User configurable memory system having local and global memory blocks
- Patent number 6,662,285
- Issue date Dec 9, 2003
- Xilinx, Inc.
- Stephen M. Douglass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User configurable on-chip memory system
- Patent number 6,522,167
- Issue date Feb 18, 2003
- Xilinx, Inc.
- Ahmad R. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed configuration independent programmable macrocell
- Patent number RE37577
- Issue date Mar 12, 2002
- Cypress Semiconductor Corporation
- Lin-Shih Liu
- 326 - Electronic digital logic circuitry
Information Patent Grant
Methods for maximizing routability in a programmable interconnect m...
- Patent number 6,243,664
- Issue date Jun 5, 2001
- Cypress Semiconductor Corporation
- Hagop A. Nazarian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for maximizing routability in a programmable interconnect m...
- Patent number 5,923,868
- Issue date Jul 13, 1999
- Cypress Semiconductor Corp.
- Hagop A. Nazarian
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods for maximizing routability in a programmable interconnect m...
- Patent number 5,848,066
- Issue date Dec 8, 1998
- Cypress Semiconductor Corp.
- Hagop A. Nazarian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
OR array architecture for a programmable logic device
- Patent number 5,701,092
- Issue date Dec 23, 1997
- Cypress Semiconductor Corp.
- Norman P. Taffe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for maximizing routability in a programmable interconnect m...
- Patent number 5,689,686
- Issue date Nov 18, 1997
- Cypress Semiconductor Corp.
- Hagop A. Nazarian
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High speed configuration independent programmable macrocell
- Patent number 5,621,338
- Issue date Apr 15, 1997
- Cypress Semiconductor Corp.
- Lin-Shih Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed configuration independent programmable macrocell
- Patent number 5,502,403
- Issue date Mar 26, 1996
- Cypress Semiconductor Corp.
- Lin-Shih Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
OR array architecture for a programmable logic device
- Patent number 5,467,029
- Issue date Nov 14, 1995
- Cypress Semiconductor Corp.
- Norman P. Taffe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture of high speed synchronous state machine
- Patent number 5,023,484
- Issue date Jun 11, 1991
- Cypress Semiconductor Corporation
- Jagdish Pathak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual I/O macrocell for high speed synchronous state machine
- Patent number 4,879,481
- Issue date Nov 7, 1989
- Cypress Semiconductor Corporation
- Jagdish Pathak
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for processing data within a programmable gate...
- Publication number 20050149695
- Publication date Jul 7, 2005
- Xilinx, Inc.
- Stephen M. Douglass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable gate array and embedded circuitry initialization and p...
- Publication number 20050040850
- Publication date Feb 24, 2005
- Xilinx, Inc.
- David P. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable gate array having interconnecting logic to support emb...
- Publication number 20030062922
- Publication date Apr 3, 2003
- Xilinx, Inc.
- Stephen M. Douglass
- G06 - COMPUTING CALCULATING COUNTING

Stephen M. Douglass

Person

Patents Grantslast 30 patents

Configurable logic fabric including two fixed logic processors with...

Programmable gate array and embedded circuitry initialization and p...

Testing of an integrated circuit having an embedded processor

Testing of an integrated circuit having an embedded processor

Speed verification of an embedded processor in a programmable logic...

Method and apparatus for processing data with a programmable gate a...

Method of designing integrated circuit having both configurable and...

Custom code processing in PGA by providing instructions from fixed...

Programmable gate array having interconnecting logic to support emb...

Floor planning for programmable gate array having embedded fixed lo...

User configurable memory system having local and global memory blocks

User configurable on-chip memory system

High speed configuration independent programmable macrocell

Methods for maximizing routability in a programmable interconnect m...

Methods for maximizing routability in a programmable interconnect m...

Methods for maximizing routability in a programmable interconnect m...

OR array architecture for a programmable logic device

Methods for maximizing routability in a programmable interconnect m...

High speed configuration independent programmable macrocell

High speed configuration independent programmable macrocell

OR array architecture for a programmable logic device

Architecture of high speed synchronous state machine

Dual I/O macrocell for high speed synchronous state machine

Patents Applicationslast 30 patents

Method and apparatus for processing data within a programmable gate...

Programmable gate array and embedded circuitry initialization and p...

Programmable gate array having interconnecting logic to support emb...