Sudip K. Nag

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Determination of path delays in circuit designs
- Patent number 9,405,871
- Issue date Aug 2, 2016
- Xilinx, Inc.
- Nagaraj Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing sub-circuits with predictable behavior within a circui...
- Patent number 8,448,122
- Issue date May 21, 2013
- Xilinx, Inc.
- Vishal Suthar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic cells with local connections
- Patent number 7,728,623
- Issue date Jun 1, 2010
- Agate Logic, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for facilitating signal routing within a progr...
- Patent number 7,725,868
- Issue date May 25, 2010
- Xilinx, Inc.
- Vinay Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic cells with local connections
- Patent number 7,605,605
- Issue date Oct 20, 2009
- Cswitch Corporation
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile multiplexer-structures in programmable logic using serial...
- Patent number 7,428,722
- Issue date Sep 23, 2008
- Cswitch Corporation
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Unified placer infrastructure
- Patent number 7,398,496
- Issue date Jul 8, 2008
- Xilinx, Inc.
- James L. Saunders
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Versatile multiplexer-structures in programmable logic using serial...
- Patent number 7,358,761
- Issue date Apr 15, 2008
- Csitch Corporation
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for facilitating signal routing within a progr...
- Patent number 7,306,977
- Issue date Dec 11, 2007
- Xilinx, Inc.
- Vinay Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated local clock placement for FPGA designs
- Patent number 7,240,315
- Issue date Jul 3, 2007
- Xilinx, Inc.
- Qiang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for timing characterization of integrated circ...
- Patent number 7,143,378
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Sudip K. Nag
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for application of network flow techniques under constraints
- Patent number 7,143,380
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using router feedback for placement improvements for logic design
- Patent number 7,076,758
- Issue date Jul 11, 2006
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Relocation of components for post-placement optimization
- Patent number 7,072,815
- Issue date Jul 4, 2006
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Upper-bound calculation for placed circuit design performance
- Patent number 7,051,312
- Issue date May 23, 2006
- Xilinx, Inc.
- Anirban Rahut
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified placer infrastructure
- Patent number 6,983,439
- Issue date Jan 3, 2006
- Xilinx, Inc.
- James L. Saunders
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing routability
- Patent number 6,877,040
- Issue date Apr 5, 2005
- Xilinx, Inc.
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of objects with partial shape restriction
- Patent number 6,857,115
- Issue date Feb 15, 2005
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of clock objects under constraints
- Patent number 6,789,244
- Issue date Sep 7, 2004
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect routing using logic levels
- Patent number 6,766,504
- Issue date Jul 20, 2004
- Xilinx, Inc.
- Anirban Rahut
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for improving PIP coverage in programmable log...
- Patent number 6,732,349
- Issue date May 4, 2004
- Xilinx, Inc.
- Richard Yachyang Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for RAM-partitioning to exploit parallelism of RA...
- Patent number 6,711,600
- Issue date Mar 23, 2004
- Xilinx, Inc.
- Hare K. Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for placement of input-output design objects i...
- Patent number 6,625,795
- Issue date Sep 23, 2003
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for RAM-partitioning to exploit parallelism of RA...
- Patent number 6,507,860
- Issue date Jan 14, 2003
- Xilinx, Inc.
- Hare K. Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for automatic timing-driven implementation of...
- Patent number 6,484,298
- Issue date Nov 19, 2002
- Xilinx, Inc.
- Sudip K. Nag
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for analytical placement of cells using density surface repr...
- Patent number 6,415,425
- Issue date Jul 2, 2002
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for RAM-partitioning to exploit parallelism of RA...
- Patent number 6,317,768
- Issue date Nov 13, 2001
- Xilinx, Inc.
- Hare K. Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of input-output design objects into a programmable gate a...
- Patent number 6,289,496
- Issue date Sep 11, 2001
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for RAM-partitioning to exploit parallelism of ra...
- Patent number 6,167,416
- Issue date Dec 26, 2000
- Xilinx, Inc.
- Hare K. Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core-based placement and annealing methods for programmable logic d...
- Patent number 6,099,583
- Issue date Aug 8, 2000
- Xilinx, Inc.
- Sudip K. Nag
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Versatile multiplexer-structures in programmable logic using serial...
- Publication number 20080129334
- Publication date Jun 5, 2008
- Cswitch Corporation
- Ravi Sunkavalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable Logic Cells with Local Connections
- Publication number 20070085564
- Publication date Apr 19, 2007
- Velogix, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic cells with Local Connections
- Publication number 20060164120
- Publication date Jul 27, 2006
- Flexlogics, Inc.
- Hare K. Verma
- H03 - BASIC ELECTRONIC CIRCUITRY

Sudip K. Nag

Person

Patents Grantslast 30 patents

Determination of path delays in circuit designs

Implementing sub-circuits with predictable behavior within a circui...

Programmable logic cells with local connections

Method and apparatus for facilitating signal routing within a progr...

Programmable logic cells with local connections

Versatile multiplexer-structures in programmable logic using serial...

Unified placer infrastructure

Versatile multiplexer-structures in programmable logic using serial...

Method and apparatus for facilitating signal routing within a progr...

Automated local clock placement for FPGA designs

Method and apparatus for timing characterization of integrated circ...

Method for application of network flow techniques under constraints

Using router feedback for placement improvements for logic design

Relocation of components for post-placement optimization

Upper-bound calculation for placed circuit design performance

Unified placer infrastructure

Method and apparatus for testing routability

Placement of objects with partial shape restriction

Placement of clock objects under constraints

Interconnect routing using logic levels

Method and apparatus for improving PIP coverage in programmable log...

System and method for RAM-partitioning to exploit parallelism of RA...

Method and apparatus for placement of input-output design objects i...

System and method for RAM-partitioning to exploit parallelism of RA...

Method and apparatus for automatic timing-driven implementation of...

Method for analytical placement of cells using density surface repr...

System and method for RAM-partitioning to exploit parallelism of RA...

Placement of input-output design objects into a programmable gate a...

System and method for RAM-partitioning to exploit parallelism of ra...

Core-based placement and annealing methods for programmable logic d...

Patents Applicationslast 30 patents

Versatile multiplexer-structures in programmable logic using serial...

Programmable Logic Cells with Local Connections

Programmable logic cells with Local Connections