Syuso Fujii

Person

Kanagawa, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Substrate structure of semi-conductor device
- Patent number 6,104,233
- Issue date Aug 15, 2000
- Kabushiki Kaisha Toshiba
- Syuso Fujii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device having cell array divided into a plural...
- Patent number 5,970,006
- Issue date Oct 19, 1999
- Kabushiki Kaisha Toshiba
- Kenji Numata
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having input protection circuit
- Patent number 5,949,109
- Issue date Sep 7, 1999
- Kabushiki Kaisha Toshiba
- Mitsuru Shimizu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device having cell array divided into a plural...
- Patent number 5,862,090
- Issue date Jan 19, 1999
- Kabushiki Kaisha Toshiba
- Kenji Numata
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having cell array divided into a plural...
- Patent number 5,734,619
- Issue date Mar 31, 1998
- Kabushiki Kaisha Toshiba
- Kenji Numata
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having different impurity concentration wells
- Patent number 5,726,475
- Issue date Mar 10, 1998
- Kabushiki Kaisha Toshiba
- Shizuo Sawada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Input protection circuit formed in a semiconductor substrate
- Patent number 5,594,265
- Issue date Jan 14, 1997
- Kabushiki Kaisha Toshiba
- Mitsuru Shimizu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory apparatus with configured word lines to reduce...
- Patent number 5,420,816
- Issue date May 30, 1995
- Kabushiki Kaisha Toshiba
- Masaki Ogihara
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having different impurity concentration wells
- Patent number 5,374,838
- Issue date Dec 20, 1994
- Kabushiki Kaisha Toshiba
- Shizuo Sawada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit device
- Patent number 5,293,055
- Issue date Mar 8, 1994
- Kabushiki Kaisha Toshiba
- Takahiko Hara
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having different impurity concentration wells
- Patent number 5,260,226
- Issue date Nov 9, 1993
- Kabushiki Kaisha Toshiba
- Shizuo Sawada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having different impurity concentration wells
- Patent number 5,238,860
- Issue date Aug 24, 1993
- Kabushiki Kaisha Toshiba
- Shizuo Sawada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device capable of directly reading the potenti...
- Patent number 5,233,558
- Issue date Aug 3, 1993
- Kabushiki Kaisha Toshiba
- Syuso Fujii
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,231,607
- Issue date Jul 27, 1993
- Kabushiki Kaisha Toshiba
- Munehiro Yoshida
- G11 - INFORMATION STORAGE
Information Patent Grant
MOS-type charging circuit
- Patent number 5,194,762
- Issue date Mar 16, 1993
- Kabushiki Kaisha Toshiba
- Takahiko Hara
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference voltage generating circuit device
- Patent number 5,150,188
- Issue date Sep 22, 1992
- Kabushiki Kaisha Toshiba
- Takahiko Hara
- G05 - CONTROLLING REGULATING
Information Patent Grant
Semiconductor memory device
- Patent number 5,142,492
- Issue date Aug 25, 1992
- Kabushiki Kaisha Toshiba
- Mitsuru Shimizu
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having burn-in test function
- Patent number 5,119,337
- Issue date Jun 2, 1992
- Kabushiki Kaisha Toshiba
- Mitsuru Shimizu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device having different impurity concentration wells
- Patent number 5,079,613
- Issue date Jan 7, 1992
- Kabushiki Kaisha Toshiba
- Shizuo Sawada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bi-CMOS semiconductor device having memory cells formed in isolated...
- Patent number 5,075,752
- Issue date Dec 24, 1991
- Kabushiki Kaisha Toshiba
- Takeo Maeda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 5,066,997
- Issue date Nov 19, 1991
- Kabushiki Kaisha Toshiba
- Kiyofumi Sakurai
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit including an intrinsic MOS transis...
- Patent number 5,041,893
- Issue date Aug 20, 1991
- Kanushiki Kaisha Toshiba
- Takeshi Nagai
- G05 - CONTROLLING REGULATING
Information Patent Grant
TTL to CMOS buffer circuit
- Patent number 5,019,729
- Issue date May 28, 1991
- Kabushiki Kaisha Toshiba
- Tohru Kimura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic memory device
- Patent number 5,016,071
- Issue date May 14, 1991
- Kabushiki Kaisha Toshiba
- Jumpei Kumagai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device
- Patent number 5,016,224
- Issue date May 14, 1991
- Kabushiki Kaisha Toshiba
- Hiroto Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Input protection circuit for semiconductor integrated circuit device
- Patent number 4,994,874
- Issue date Feb 19, 1991
- Kabushiki Kaisha Toshiba
- Mitsuru Shimizu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic memory device with improved wiring layer layout
- Patent number 4,941,031
- Issue date Jul 10, 1990
- Kabushiki Kaisha Toshiba
- Jumpei Kumagai
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory having barrier transistors connected between s...
- Patent number 4,931,992
- Issue date Jun 5, 1990
- Kabushiki Kaisha Toshiba
- Masaki Ogihara
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit technology for eliminating circuit...
- Patent number 4,896,055
- Issue date Jan 23, 1990
- Kabushiki Kaisha Toshiba
- Syuso Fujii
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device with voltage bootstrap
- Patent number 4,769,792
- Issue date Sep 6, 1988
- Kabushiki Kaisha Toshiba
- Kazutaka Nogami
- G11 - INFORMATION STORAGE

Syuso Fujii

Person

Patents Grantslast 30 patents

Substrate structure of semi-conductor device

Semiconductor memory device having cell array divided into a plural...

Semiconductor device having input protection circuit

Semiconductor memory device having cell array divided into a plural...

Semiconductor memory device having cell array divided into a plural...

Semiconductor device having different impurity concentration wells

Input protection circuit formed in a semiconductor substrate

Semiconductor memory apparatus with configured word lines to reduce...

Semiconductor device having different impurity concentration wells

Semiconductor integrated circuit device

Semiconductor device having different impurity concentration wells

Semiconductor device having different impurity concentration wells

Semiconductor memory device capable of directly reading the potenti...

Semiconductor memory device

MOS-type charging circuit

Reference voltage generating circuit device

Semiconductor memory device

Semiconductor memory device having burn-in test function

Semiconductor device having different impurity concentration wells

Bi-CMOS semiconductor device having memory cells formed in isolated...

Semiconductor device

Semiconductor integrated circuit including an intrinsic MOS transis...

TTL to CMOS buffer circuit

Dynamic memory device

Semiconductor memory device

Input protection circuit for semiconductor integrated circuit device

Dynamic memory device with improved wiring layer layout

Semiconductor memory having barrier transistors connected between s...

Semiconductor integrated circuit technology for eliminating circuit...

Semiconductor memory device with voltage bootstrap