Szu-chun TSAO

Person

Su'ao Township, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Dummy device for core device to operate in a safe operating area an...
- Patent number 12,183,731
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Szu-Chun Tsao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDO/band gap reference circuit
- Patent number 12,147,255
- Issue date Nov 19, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Szu-Chun Tsao
- G05 - CONTROLLING REGULATING
Information Patent Grant
System and method for reliable sensing of memory cells
- Patent number 12,106,809
- Issue date Oct 1, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital low-dropout voltage regulator
- Patent number 12,093,065
- Issue date Sep 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Yu Lai
- G05 - CONTROLLING REGULATING
Information Patent Grant
Device and method for reading data in memory
- Patent number 12,087,389
- Issue date Sep 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jaw-Juinn Horng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias control for memory cells with multiple gate electrodes
- Patent number 12,057,177
- Issue date Aug 6, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-dropout (LDO) voltage regulator including amplifier and decoupl...
- Patent number 11,906,997
- Issue date Feb 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Szu-Chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SRAM architecture for convolutional neural network application
- Patent number 11,853,880
- Issue date Dec 26, 2023
- Taiwan Semiconductor Manufacturing Company Limited
- Jaw-Juinn Horng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for reliable sensing of memory cells
- Patent number 11,763,891
- Issue date Sep 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital low-dropout voltage regulator
- Patent number 11,733,724
- Issue date Aug 22, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Yu Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and method for stepping down a voltage
- Patent number 11,726,510
- Issue date Aug 15, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bindu Madhavi Kasina
- G05 - CONTROLLING REGULATING
Information Patent Grant
LDO/band gap reference circuit
- Patent number 11,669,115
- Issue date Jun 6, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Szu-Chun Tsao
- G05 - CONTROLLING REGULATING
Information Patent Grant
Device and method for reading data in memory
- Patent number 11,430,491
- Issue date Aug 30, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jaw-Juinn Horng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias control for memory cells with multiple gate electrodes
- Patent number 11,257,550
- Issue date Feb 22, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse width modulation output stage with dead time control
- Patent number 10,958,259
- Issue date Mar 23, 2021
- Elite Semiconductor Memory Technology Inc.
- Szu-Chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Quaternary/ternary modulation selecting circuit and associated method
- Patent number 10,404,227
- Issue date Sep 3, 2019
- Elite Semiconductor Memory Technology Inc.
- Szu-Chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus with load dump protection
- Patent number 10,050,432
- Issue date Aug 14, 2018
- Elite Semiconductor Memory Technology Inc
- Szu-chun Tsao
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Clock generating circuit and associated method
- Patent number 9,977,459
- Issue date May 22, 2018
- Elite Semiconductor Memory Technology Inc.
- Chin-Tung Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable gain amplifying circuit
- Patent number 9,748,911
- Issue date Aug 29, 2017
- Elite Semiconductor Memory Technology Inc.
- Szu-chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Protection circuit for preventing an over-current from an output stage
- Patent number 9,705,315
- Issue date Jul 11, 2017
- Elite Semiconductor Memory Technology Inc.
- Szu-Chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Triangular wave generating circuit to provide clock synchronization
- Patent number 9,300,281
- Issue date Mar 29, 2016
- Elite Semiconductor Memory Technology Inc.
- Szu-chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LDO/Band Gap Reference Circuit
- Publication number 20250044819
- Publication date Feb 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- G05 - CONTROLLING REGULATING
Information Patent Application
SYSTEM AND METHOD FOR RELIABLE SENSING OF MEMORY CELLS
- Publication number 20240386968
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Application
DUMMY DEVICE FOR CORE DEVICE TO OPERATE IN A SAFE OPERATING AREA AN...
- Publication number 20240379665
- Publication date Nov 14, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- SZU-CHUN TSAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE AND METHOD FOR READING DATA IN MEMORY
- Publication number 20240371420
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaw-Juinn Horng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL LOW-DROPOUT VOLTAGE REGULATOR
- Publication number 20240370045
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Yu LAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES
- Publication number 20240355398
- Publication date Oct 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Application
LOW-DROPOUT (LDO) VOLTAGE REGULATOR
- Publication number 20240143008
- Publication date May 2, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL LOW-DROPOUT VOLTAGE REGULATOR
- Publication number 20240085934
- Publication date Mar 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Yu LAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM ARCHITECTURE FOR CONVOLUTIONAL NEURAL NETWORK APPLICATION
- Publication number 20240086708
- Publication date Mar 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaw-Juinn Horng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR RELIABLE SENSING OF MEMORY CELLS
- Publication number 20230377661
- Publication date Nov 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit and Method for Stepping Down a Voltage
- Publication number 20230350442
- Publication date Nov 2, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bindu Madhavi Kasina
- G05 - CONTROLLING REGULATING
Information Patent Application
LDO/Band Gap Reference Circuit
- Publication number 20230244258
- Publication date Aug 3, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- G05 - CONTROLLING REGULATING
Information Patent Application
LDO/Band Gap Reference Circuit
- Publication number 20230063492
- Publication date Mar 2, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- G05 - CONTROLLING REGULATING
Information Patent Application
CIRCUIT AND METHOD FOR STEPPING DOWN A VOLTAGE
- Publication number 20230064967
- Publication date Mar 2, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bindu Madhavi Kasina
- G05 - CONTROLLING REGULATING
Information Patent Application
DIGITAL LOW-DROPOUT VOLTAGE REGULATOR
- Publication number 20230053710
- Publication date Feb 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Yu Lai
- G05 - CONTROLLING REGULATING
Information Patent Application
Systems and Methods for Providing A Dynamic High Voltage Circuit De...
- Publication number 20230023317
- Publication date Jan 26, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shenggao Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE AND METHOD FOR READING DATA IN MEMORY
- Publication number 20220366948
- Publication date Nov 17, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaw-Juinn Horng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-DROPOUT (LDO) VOLTAGE REGULATOR
- Publication number 20220365550
- Publication date Nov 17, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUMMY DEVICE FOR CORE DEVICE TO OPERATE IN A SAFE OPERATING AREA AN...
- Publication number 20220231014
- Publication date Jul 21, 2022
- Taiwan Semiconductor Manufacturing company Ltd.
- SZU-CHUN TSAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES
- Publication number 20220130470
- Publication date Apr 28, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM ARCHITECTURE FOR CONVOLUTIONAL NEURAL NETWORK APPLICATION
- Publication number 20220067501
- Publication date Mar 3, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Jaw-Juinn Horng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES
- Publication number 20210391021
- Publication date Dec 16, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR RELIABLE SENSING OF MEMORY CELLS
- Publication number 20210375370
- Publication date Dec 2, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Szu-Chun Tsao
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE AND METHOD FOR READING DATA IN MEMORY
- Publication number 20210343320
- Publication date Nov 4, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaw-Juinn Horng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSE WIDTH MODULATION OUTPUT STAGE WITH DEAD TIME CONTROL
- Publication number 20200389161
- Publication date Dec 10, 2020
- ELITE SEMICONDUCTOR MEMORY TECHNOLOGY Inc.
- Szu-chun TSAO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
QUATERNARY/TERNARY MODULATION SELECTING CIRCUIT AND ASSOCIATED METHOD
- Publication number 20190288652
- Publication date Sep 19, 2019
- ELITE SEMICONDUCTOR MEMORY TECHNOLOGY Inc.
- Szu-Chun Tsao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS WITH LOAD DUMP PROTECTION
- Publication number 20170358918
- Publication date Dec 14, 2017
- Elite Semiconductor Memory Technology Inc.
- Szu-chun TSAO
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
VARIABLE GAIN AMPLIFYING CIRCUIT
- Publication number 20170201220
- Publication date Jul 13, 2017
- ELITE SEMICONDUCTOR MEMORY TECHNOLOGY Inc.
- Szu-chun TSAO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROTECTION CIRCUIT FOR PREVENTING AN OVER-CURRENT FROM AN OUTPUT STAGE
- Publication number 20160308352
- Publication date Oct 20, 2016
- ELITE SEMICONDUCTOR MEMORY TECHNOLOGY Inc.
- Szu-Chun Tsao
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
TRIANGULAR WAVE GENERATING CIRCUIT TO PROVIDE CLOCK SYNCHRONIZATION
- Publication number 20150200659
- Publication date Jul 16, 2015
- Elite Semiconductor Memory Technology Inc.
- Szu-chun TSAO
- H03 - BASIC ELECTRONIC CIRCUITRY

Szu-chun TSAO

Person

Patents Grantslast 30 patents

Dummy device for core device to operate in a safe operating area an...

LDO/band gap reference circuit

System and method for reliable sensing of memory cells

Digital low-dropout voltage regulator

Device and method for reading data in memory

Bias control for memory cells with multiple gate electrodes

Low-dropout (LDO) voltage regulator including amplifier and decoupl...

SRAM architecture for convolutional neural network application

System and method for reliable sensing of memory cells

Digital low-dropout voltage regulator

Circuit and method for stepping down a voltage

LDO/band gap reference circuit

Device and method for reading data in memory

Bias control for memory cells with multiple gate electrodes

Pulse width modulation output stage with dead time control

Quaternary/ternary modulation selecting circuit and associated method

Apparatus with load dump protection

Clock generating circuit and associated method

Variable gain amplifying circuit

Protection circuit for preventing an over-current from an output stage

Triangular wave generating circuit to provide clock synchronization

Patents Applicationslast 30 patents

LDO/Band Gap Reference Circuit

SYSTEM AND METHOD FOR RELIABLE SENSING OF MEMORY CELLS

DUMMY DEVICE FOR CORE DEVICE TO OPERATE IN A SAFE OPERATING AREA AN...

DEVICE AND METHOD FOR READING DATA IN MEMORY

DIGITAL LOW-DROPOUT VOLTAGE REGULATOR

BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES

LOW-DROPOUT (LDO) VOLTAGE REGULATOR

DIGITAL LOW-DROPOUT VOLTAGE REGULATOR

SRAM ARCHITECTURE FOR CONVOLUTIONAL NEURAL NETWORK APPLICATION

SYSTEM AND METHOD FOR RELIABLE SENSING OF MEMORY CELLS

Circuit and Method for Stepping Down a Voltage

LDO/Band Gap Reference Circuit

LDO/Band Gap Reference Circuit

CIRCUIT AND METHOD FOR STEPPING DOWN A VOLTAGE

DIGITAL LOW-DROPOUT VOLTAGE REGULATOR

Systems and Methods for Providing A Dynamic High Voltage Circuit De...

DEVICE AND METHOD FOR READING DATA IN MEMORY

LOW-DROPOUT (LDO) VOLTAGE REGULATOR

DUMMY DEVICE FOR CORE DEVICE TO OPERATE IN A SAFE OPERATING AREA AN...

BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES

SRAM ARCHITECTURE FOR CONVOLUTIONAL NEURAL NETWORK APPLICATION

BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES

SYSTEM AND METHOD FOR RELIABLE SENSING OF MEMORY CELLS

DEVICE AND METHOD FOR READING DATA IN MEMORY

PULSE WIDTH MODULATION OUTPUT STAGE WITH DEAD TIME CONTROL

QUATERNARY/TERNARY MODULATION SELECTING CIRCUIT AND ASSOCIATED METHOD

APPARATUS WITH LOAD DUMP PROTECTION

VARIABLE GAIN AMPLIFYING CIRCUIT

PROTECTION CIRCUIT FOR PREVENTING AN OVER-CURRENT FROM AN OUTPUT STAGE

TRIANGULAR WAVE GENERATING CIRCUIT TO PROVIDE CLOCK SYNCHRONIZATION