Tae Jong Lee

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Slot designs in wide metal lines
- Patent number 9,318,378
- Issue date Apr 19, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Grain boundary blocking for stress migration and electromigration i...
- Patent number 7,989,338
- Issue date Aug 2, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Fan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Combined copper plating method to improve gap fill
- Patent number 7,585,768
- Issue date Sep 8, 2009
- Chartered Semiconductor Manufacturing, Ltd.
- Xiaomei Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate aligned dual damascene openings
- Patent number 7,372,156
- Issue date May 13, 2008
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabrication of a die oxide ring
- Patent number 7,276,440
- Issue date Oct 2, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Fan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system using dual damascene process
- Patent number 7,253,097
- Issue date Aug 7, 2007
- Chartered Semiconductor Manufacturing, Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with protective moat
- Patent number 7,224,060
- Issue date May 29, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Fan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of liner air gap formation
- Patent number 7,094,669
- Issue date Aug 22, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Xiaomei Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate aligned dual damascene openings
- Patent number 6,967,156
- Issue date Nov 22, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicon-on-insulator device wafer die
- Patent number 6,849,928
- Issue date Feb 1, 2005
- Chartered Semiconductor Manufacturing, Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicon-on-insulator device wafer die
- Patent number 6,558,994
- Issue date May 6, 2003
- Chartered Semiconductors Maufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified method to reduce or eliminate STI oxide divots
- Patent number 6,432,797
- Issue date Aug 13, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Effective retardation of fluorine radical attack on metal lines via...
- Patent number 6,376,360
- Issue date Apr 23, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for a short channel CMOS transistor with small overlay capac...
- Patent number 6,348,385
- Issue date Feb 19, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to eliminate top metal corner shaping during bottom metal pa...
- Patent number 6,284,590
- Issue date Sep 4, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SLOT DESIGNS IN WIDE METAL LINES
- Publication number 20160233157
- Publication date Aug 11, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Yeow Kheng LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Combined copper plating method to improve gap fill
- Publication number 20070293039
- Publication date Dec 20, 2007
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Xiaomei Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
- Publication number 20070111397
- Publication date May 17, 2007
- STATS ChipPAC Ltd.
- Minseok Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE SYSTEM WITH THERMAL DIE BONDING
- Publication number 20070108590
- Publication date May 17, 2007
- STATS ChipPAC Ltd.
- Sangkwon Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG
- Publication number 20070108596
- Publication date May 17, 2007
- STATS ChipPAC Ltd.
- Kyungsic Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS
- Publication number 20070001303
- Publication date Jan 4, 2007
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Grain boundary blocking for stress migration and electromigration i...
- Publication number 20060286797
- Publication date Dec 21, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Fan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG
- Publication number 20060103009
- Publication date May 18, 2006
- STATS ChipPAC Ltd.
- Seongmin Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Slot designs in wide metal lines
- Publication number 20060040491
- Publication date Feb 23, 2006
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method of liner air gap formation
- Publication number 20060030128
- Publication date Feb 9, 2006
- Xiaomei Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to fabricate aligned dual damacene openings
- Publication number 20060003573
- Publication date Jan 5, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductive compound cap layer
- Publication number 20060001170
- Publication date Jan 5, 2006
- Fan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with protective moat
- Publication number 20050167824
- Publication date Aug 4, 2005
- Chartered Semiconductor Manufacturing LTD.
- Fan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabrication of a die oxide ring
- Publication number 20050127495
- Publication date Jun 16, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Fan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to fabricate aligned dual damascene openings
- Publication number 20050090095
- Publication date Apr 28, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual silicon-on-insulator device wafer die
- Publication number 20030107083
- Publication date Jun 12, 2003
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual silicon-on-insulator device wafer die
- Publication number 20020127816
- Publication date Sep 12, 2002
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIMPLIFIED METHOD TO REDUCE OR ELIMINATE STI OXIDE DIVOTS
- Publication number 20020098661
- Publication date Jul 25, 2002
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS

Tae Jong Lee

Person

Patents Grantslast 30 patents

Slot designs in wide metal lines

Grain boundary blocking for stress migration and electromigration i...

Combined copper plating method to improve gap fill

Method to fabricate aligned dual damascene openings

Method of fabrication of a die oxide ring

Integrated circuit system using dual damascene process

Integrated circuit with protective moat

Structure and method of liner air gap formation

Method to fabricate aligned dual damascene openings

Dual silicon-on-insulator device wafer die

Dual silicon-on-insulator device wafer die

Simplified method to reduce or eliminate STI oxide divots

Effective retardation of fluorine radical attack on metal lines via...

Method for a short channel CMOS transistor with small overlay capac...

Method to eliminate top metal corner shaping during bottom metal pa...

Patents Applicationslast 30 patents

SLOT DESIGNS IN WIDE METAL LINES

Combined copper plating method to improve gap fill

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK

SEMICONDUCTOR PACKAGE SYSTEM WITH THERMAL DIE BONDING

INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG

INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS

Grain boundary blocking for stress migration and electromigration i...

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG

Slot designs in wide metal lines

Structure and method of liner air gap formation

Method to fabricate aligned dual damacene openings

Conductive compound cap layer

Integrated circuit with protective moat

Method of fabrication of a die oxide ring

Method to fabricate aligned dual damascene openings

Dual silicon-on-insulator device wafer die

Dual silicon-on-insulator device wafer die

SIMPLIFIED METHOD TO REDUCE OR ELIMINATE STI OXIDE DIVOTS