Patent Application
20070293039
In the accompanying drawing forming a material part of this description, there is shown:
To fabricate the (n+1)th copper interconnect level a blanket IMD layer, 10, the (n+1)th IMD layer, is formed over the insulator capping layer of the nth copper interconnect level. The IMD layer could be composed of oxide, nitride or oxynitride or of low dielectric constant materials such as polyimide, PTFE, amorphous fluorocarbon or fluorinated SiO2 whose thickness could be between about 0.3 to about 1.5 micrometers. There are abundant conventional processes, which are well known to practitioners of the art, to form IMD layers. Besides trench-first processes, such as those described in detail, there are via first processes that are commonly used for advanced technology beyond 0.13 micrometers. As in conventional dual damascene processes, gaps are formed in two stages. First, the IMD is patterned and etched to form trenches, 12, and the wide portions, 14, of via regions. The depth of regions 12 and 14, which is the depth of the metal lines that fill these regions, is about 0.2 to about 1.5 micrometers. Metal line depths are between about 0.1 to 0.5 micrometers and via regions are between about 0.2 to 1.5 micrometers deep. This patterning and etching can be accomplished conventionally; for example, by forming a photoresist layer over the IMD layer, patterning the photoresist layer and etching to form the regions 12 and 14, and removing the photoresist layer. In the second stage IMD is removed only from via gaps, 16, to the top of the nth copper layer, 4. Thus the nth insulator capping layer, 8, is removed in via gaps so the bottom of via gaps reaches to the top of the nth copper layer, 4. The depth of via gaps is just the difference between the IMD layer thickness and the depth of the trenches, 12. Thus via gap depths are between about 0.2 to about 1.0 micrometers. At via regions the total gap depth is just the thickness of the IMD layer and since line widths in present and near future technologies are between about 0.3 to about 1.5 micrometers, aspect ratios between about 4 to about 10 are to be encountered. As in the first stage, the patterning and etching can be accomplished conventionally. For example, forming a photoresist layer over the IMD layer, patterning the photoresist layer and etching to form the regions 16, and removing the photoresist layer is a conventional process that can accomplish it. A blanket conformal metal barrier layer, 18, is then formed. Metal barrier layer, 18, serves to prevent copper migration and should be comprised out of materials that act as good diffusion barriers. Effective barrier layers are established by layers of between about 50 to about 300 Angstroms comprised of materials such as TiN, Ta or TaN. The structure at this stage of the process is shown in
Filling of the gaps with copper commences at this stage.
Next a partial filling of the deeper portions of gaps, which in the case of dual damascene are the via gap regions 16, is accomplished by electroless plating of copper. This is a crucial step in the invention in which the effective aspect ratios of deeper gaps are reduced so that ECP could be used to complete the copper filling of the gaps. This is important since ECP is the more economical and efficient copper filling process, and with the deeper portions of the gaps partially filled, pinhole like voids will not form. In one embodiment, the partial filling of the deeper portions of gaps is achieved by utilizing water jet technology to blow away plating solution except from regions 16, so that the solution is as indicated by regions 22 in
Performing electroless plating with the solution in the via gap regions, 16, results in a partial copper filling of the via gap regions thus forming electroless copper regions 24 shown in
A conventional annealing step can now be performed to anneal the copper, in which a temperature of about 150° C. is usually used for duration of about 0.5 hours. A CMP step follows to planarize the surface, giving rise to the copper regions 28. Finally an insulator capping layer 30 is formed to prevent copper migration into the IMD. The insulator capping layer should be comprised of a good diffusion barrier material, such as silicon carbide or silicon nitride of thickness between about 200 to about 800 Angstroms.
While the detailed description of preferred embodiments of the invention is given for the case of dual damascene, in which the high aspect ratio features are associated with via regions, the applicability of the invention for any high aspect ratio gaps is apparent. For lower aspect ratio gaps ECP, being more efficient and economic, is the copper filling process of choice. Electroless copper plating does not give rise to pinhole like voids even for high aspect ratio gaps, but it is a low throughput and high cost process. By utilizing features of both electroless copper plating and ECP, preferred embodiments of the invention provide processes that achieve gap filling that is free of pinhole-like voids even for high aspect ratio gaps and that is at the same time efficient and economic. In the methods of the invention electroless copper plating is used to form a copper layer sufficient to reduce the gap aspect ratio to a degree so that ECP can be used to complete the gap filling without introducing pinhole-like voids. Thus the low throughput and high cost arising from the electroless copper plating process is minimized. In preferred embodiments of the invention electroless copper plating is used only to the extent that is required to reduce the gap depth sufficiently so that with the reduced depth the aspect ratio has been reduced enough so that pinhole-like voids do not occur when the more efficient and economic ECP process is used to complete the gap filling.
Thus, a wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is first formed that serves to prevent copper migration and should be comprised out of materials that act as good diffusion barriers. Effective barrier layers are established by layers of between about 50 to about 300 Angstroms comprised of materials such as TiN, Ta or TaN.
Filling of the gaps with copper commences with submerging the wafer in a solution to electroless plate a blanket conformal copper seed layer whose purpose is to promote adhesion between the bulk copper and the metal barrier layer and to serve as a nucleation layer for ECP copper. In preferred embodiments of the invention the copper seed layer is between about 50 to about 100 Angstroms thick. Next a partial filling of the deeper gaps is accomplished by electroless plating of copper. Deeper gaps are those that could give rise to pinhole like voids when conventional ECP is used as the copper filling process. This partial filling step is a crucial step in the invention. In this step the effective aspect ratios of deeper gaps are reduced so that ECP could be used to complete the copper filling of the gaps. This is important since ECP is the more economical and efficient copper filling process, and with deeper gaps already partially filled pinhole like voids will not form. There are two options for achieving a partial filling of the deeper gaps. One way is to utilize water jet technology to blow away plating solution except from the lower portions of deeper gaps. The depth of the surface of the solution is adjusted so that after electroless plating the remaining gaps all have acceptably low aspect ratios. The other option to accomplish a partial filling of the deeper gaps is to spin-on the plating solution. By tuning the speed it can be arranged so that the surface of the solution is adjusted so that after electroless plating the remaining gaps all have acceptably low aspect ratios. Performing electroless plating with the solution the lower potions of the deeper gaps results in a partial copper filling of the deeper gaps. The thickness of copper thus formed by electroless plating should be large enough so that the aspect ratios associated with the remainders of the deeper gaps are small enough that pinhole like voids do not form when ECP is used to complete the filling. The ECP process is used to complete the copper filling. A blanket copper layer is thus formed over the wafer. A conventional annealing step is then performed to anneal the copper, in which a temperature of about 150° C. is usually used for duration of about 0.5 hours. A CMP step follows to planarize the surface, giving rise to the gaps now filled with copper separated by the dielectric layer.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.
