Takaaki Furuyama

Person

Kasugai-shi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Nonvolatile memory device having a plurality of memory blocks
- Patent number 8,094,478
- Issue date Jan 10, 2012
- Spansion LLC
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Time reduction of address setup/hold time for semiconductor memory
- Patent number 8,031,537
- Issue date Oct 4, 2011
- Spansion LLC
- Makoto Niimi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for address allotting and verification in a se...
- Patent number 8,023,341
- Issue date Sep 20, 2011
- Spansion LLC
- Shozo Kawabata
- G11 - INFORMATION STORAGE
Information Patent Grant
Time reduction of address setup/hold time for semiconductor memory
- Patent number 7,889,573
- Issue date Feb 15, 2011
- Spansion LLC
- Makoto Niimi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for address allotting and verification in a se...
- Patent number 7,813,154
- Issue date Oct 12, 2010
- Spansion LLC
- Shozo Kawabata
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory device having a plurality of memory blocks
- Patent number 7,808,808
- Issue date Oct 5, 2010
- Spansion LLC
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating a semiconductor device
- Patent number 7,452,771
- Issue date Nov 18, 2008
- Fujitsu Limited
- Masaki Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for address allotting and verification in a se...
- Patent number 7,433,219
- Issue date Oct 7, 2008
- Spansion LLC
- Shozo Kawabata
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for initialization control in a non-volatile m...
- Patent number 7,415,568
- Issue date Aug 19, 2008
- Spansion LLC
- Shozo Kawabata
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and control method therefor
- Patent number 7,321,515
- Issue date Jan 22, 2008
- Spansion LLC
- Koji Shimbayashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and test method therefor
- Patent number 7,281,180
- Issue date Oct 9, 2007
- Spansion LLC
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for applying bias to a storage device
- Patent number 7,239,548
- Issue date Jul 3, 2007
- Spansion LLC
- Kenta Kato
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and write method of the same
- Patent number 7,212,443
- Issue date May 1, 2007
- Spansion LLC
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory storage device and a redundancy control method...
- Patent number 7,068,555
- Issue date Jun 27, 2006
- Spansion LLC
- Satoru Sugimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory storage device and its redundant method
- Patent number 7,061,816
- Issue date Jun 13, 2006
- Spansion LLC
- Akira Sugiura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device comprising transistors having control gates an...
- Patent number 6,977,411
- Issue date Dec 20, 2005
- Fujitsu Limited
- Masaki Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile semiconductor memory device
- Patent number 6,917,541
- Issue date Jul 12, 2005
- Fujitsu Limited
- Koji Shimbayashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold voltage adjustment method of non-volatile semiconductor m...
- Patent number 6,879,521
- Issue date Apr 12, 2005
- Fujitsu Limited
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory capable of changing bank configuration
- Patent number 6,643,758
- Issue date Nov 4, 2003
- Fujitsu Limited
- Takaaki Furuyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device and refreshing method of semiconductor...
- Patent number 6,490,215
- Issue date Dec 3, 2002
- Fujitsu Limited
- Kazufumi Komura
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for resetting a pair of data buses of a semiconductor memor...
- Patent number 6,462,997
- Issue date Oct 8, 2002
- Fujitsu Limited
- Hiroyuki Sugamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Data writing method for semiconductor memory device
- Patent number 6,310,825
- Issue date Oct 30, 2001
- Fujitsu Limited
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for resetting a pair of data buses of a semiconductor memor...
- Patent number 6,198,680
- Issue date Mar 6, 2001
- Fujitsu Limited
- Hiroyuki Sugamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Direct sensing semiconductor memory device
- Patent number 6,128,238
- Issue date Oct 3, 2000
- Fujitsu Limited
- Kenji Nagai
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM with reduced electric power consumption
- Patent number 6,097,658
- Issue date Aug 1, 2000
- Fujitsu Limited
- Yasuharu Satoh
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line multi-selection circuit for a memory device
- Patent number 5,909,407
- Issue date Jun 1, 1999
- Fujitsu Limited
- Yasuhiro Yamamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM with reduced electric power consumption
- Patent number 5,867,438
- Issue date Feb 2, 1999
- Fujitsu Limited
- Yukihiro Nomura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device provided with block write function
- Patent number 5,787,046
- Issue date Jul 28, 1998
- Fujitsu Limited
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage level detector
- Patent number 5,708,625
- Issue date Jan 13, 1998
- Fujitsu Limited
- Hajime Sato
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM with reduced electric power consumption
- Patent number 5,594,699
- Issue date Jan 14, 1997
- Fujitsu Limited
- Yukihiro Nomura
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY
- Publication number 20110103157
- Publication date May 5, 2011
- Makoto NIIMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SE...
- Publication number 20110026287
- Publication date Feb 3, 2011
- Shozo KAWABATA
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS
- Publication number 20110002177
- Publication date Jan 6, 2011
- Takaaki FURUYAMA
- G11 - INFORMATION STORAGE
Information Patent Application
TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY
- Publication number 20090323435
- Publication date Dec 31, 2009
- Makoto Niimi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS
- Publication number 20090034334
- Publication date Feb 5, 2009
- SPANSION LLC
- Takaaki FURUYAMA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SE...
- Publication number 20080316787
- Publication date Dec 25, 2008
- Shozo Kawabata
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device and control method therefor
- Publication number 20060227629
- Publication date Oct 12, 2006
- Koji Shimbayashi
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for applying bias to a storage device
- Publication number 20060227630
- Publication date Oct 12, 2006
- Kenta Kato
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for address allotting and verification in a se...
- Publication number 20060209583
- Publication date Sep 21, 2006
- Shozo Kawabata
- G11 - INFORMATION STORAGE
Information Patent Application
Method for fabricating a semiconductor device
- Publication number 20060046373
- Publication date Mar 2, 2006
- FUJITSU LIMITED
- Masaki Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for initialization control in a non-volatile m...
- Publication number 20060023500
- Publication date Feb 2, 2006
- Shozo Kawabata
- G11 - INFORMATION STORAGE
Information Patent Application
Memory system and test method therefor
- Publication number 20060002196
- Publication date Jan 5, 2006
- Spansion LLC
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory storage device and a redundancy control method...
- Publication number 20050185482
- Publication date Aug 25, 2005
- Satoru Sugimoto
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory storage device and its redundant method
- Publication number 20050185483
- Publication date Aug 25, 2005
- Akira Sugiura
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device and method for testing the same
- Publication number 20050149792
- Publication date Jul 7, 2005
- FUJITSU LIMITED
- Takaaki Furuyama
- G01 - MEASURING TESTING
Information Patent Application
Non-volatile memory and write method of the same
- Publication number 20050141277
- Publication date Jun 30, 2005
- FUJITSU LIMITED
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device and method for fabricating the same
- Publication number 20040129970
- Publication date Jul 8, 2004
- Masaki Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Threshold voltage adjustment method of non-volatile semiconductor m...
- Publication number 20040008567
- Publication date Jan 15, 2004
- FUJITSU LIMITED
- Takaaki Furuyama
- G11 - INFORMATION STORAGE
Information Patent Application
Nonvolatile semiconductor memory device
- Publication number 20030043623
- Publication date Mar 6, 2003
- FUJITSU LIMITED
- Koji Shimbayashi
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory capable of changing bank configuration
- Publication number 20020161962
- Publication date Oct 31, 2002
- FUJITSU LIMITED
- Takaaki Furuyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor memory device and refreshing method of semiconductor...
- Publication number 20010043499
- Publication date Nov 22, 2001
- FUJITSU LIMITED
- Kazufumi Komura
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit for resetting a pair of data buses of a semiconductor memor...
- Publication number 20010001261
- Publication date May 17, 2001
- FUJITSU LIMITED
- Hiroyuki Sugamoto
- G11 - INFORMATION STORAGE

Takaaki Furuyama

Person

Patents Grantslast 30 patents

Nonvolatile memory device having a plurality of memory blocks

Time reduction of address setup/hold time for semiconductor memory

Method and apparatus for address allotting and verification in a se...

Time reduction of address setup/hold time for semiconductor memory

Method and apparatus for address allotting and verification in a se...

Nonvolatile memory device having a plurality of memory blocks

Method for fabricating a semiconductor device

Method and apparatus for address allotting and verification in a se...

Method and apparatus for initialization control in a non-volatile m...

Memory device and control method therefor

Memory system and test method therefor

Method and apparatus for applying bias to a storage device

Non-volatile memory and write method of the same

Semiconductor memory storage device and a redundancy control method...

Semiconductor memory storage device and its redundant method

Semiconductor device comprising transistors having control gates an...

Nonvolatile semiconductor memory device

Threshold voltage adjustment method of non-volatile semiconductor m...

Flash memory capable of changing bank configuration

Semiconductor memory device and refreshing method of semiconductor...

Circuit for resetting a pair of data buses of a semiconductor memor...

Data writing method for semiconductor memory device

Circuit for resetting a pair of data buses of a semiconductor memor...

Direct sensing semiconductor memory device

DRAM with reduced electric power consumption

Word line multi-selection circuit for a memory device

DRAM with reduced electric power consumption

Semiconductor memory device provided with block write function

Voltage level detector

DRAM with reduced electric power consumption

Patents Applicationslast 30 patents

TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY

METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SE...

NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS

TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY

NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS

METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SE...

Memory device and control method therefor

Method and apparatus for applying bias to a storage device

Method and apparatus for address allotting and verification in a se...

Method for fabricating a semiconductor device

Method and apparatus for initialization control in a non-volatile m...

Memory system and test method therefor

Semiconductor memory storage device and a redundancy control method...

Semiconductor memory storage device and its redundant method

Semiconductor device and method for testing the same

Non-volatile memory and write method of the same

Semiconductor device and method for fabricating the same

Threshold voltage adjustment method of non-volatile semiconductor m...

Nonvolatile semiconductor memory device

Flash memory capable of changing bank configuration

Semiconductor memory device and refreshing method of semiconductor...

Circuit for resetting a pair of data buses of a semiconductor memor...