Timothy James Thurgate

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Tilted implant for poly resistors
- Patent number 11,257,675
- Issue date Feb 22, 2022
- Cypress Semiconductor Corporation
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge-trapping memory device
- Patent number 10,644,016
- Issue date May 5, 2020
- Cypress Semiconductor Corporation
- Kuo Tung Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for rounded ONO formation in a flash memory de...
- Patent number 9,564,331
- Issue date Feb 7, 2017
- Cypress Semiconductor Corporation
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device and method for biasing same
- Patent number 9,559,216
- Issue date Jan 31, 2017
- Micron Technology, Inc.
- Srinivasa Rao Banna
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for providing a semiconductor memory device
- Patent number 9,524,971
- Issue date Dec 20, 2016
- Srinivasa R. Banna
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for forming edge wordline implants adjacent edge wordlines
- Patent number 9,466,489
- Issue date Oct 11, 2016
- Cypress Semiconductor Corporation
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for manufacturing self-aligned STI with single poly
- Patent number 9,276,007
- Issue date Mar 1, 2016
- Cypress Semiconductor Corporation
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for providing a semiconductor memory device
- Patent number 9,263,133
- Issue date Feb 16, 2016
- Micron Technology, Inc.
- Srinivasa R. Banna
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for providing a semiconductor memory device
- Patent number 9,019,759
- Issue date Apr 28, 2015
- Micron Technology, Inc.
- Srinivasa R. Banna
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-aligned STI with single poly for manufacturing a flash memory...
- Patent number 8,642,441
- Issue date Feb 4, 2014
- Spansion LLC
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for providing a semiconductor memory device
- Patent number 8,547,738
- Issue date Oct 1, 2013
- Micron Technology, Inc.
- Srinivasa Rao Banna
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for providing a semiconductor memory device
- Patent number 8,531,878
- Issue date Sep 10, 2013
- Micron Technology, Inc.
- Srinivasa Rao Banna
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device protection layer
- Patent number 8,415,734
- Issue date Apr 9, 2013
- Spansion LLC
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an electronic device including forming a charge s...
- Patent number 8,409,952
- Issue date Apr 2, 2013
- Spansion LLC
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for extended nitride layer in a flash memory
- Patent number 8,208,296
- Issue date Jun 26, 2012
- Spansion LLC
- Timothy Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device with buried bit line structure
- Patent number 8,148,770
- Issue date Apr 3, 2012
- Spansion LLC
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory comprising dual charge storage nodes and metho...
- Patent number 8,076,712
- Issue date Dec 13, 2011
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective application of word line bias to minimize fringe effects...
- Patent number 7,952,938
- Issue date May 31, 2011
- Spansion LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-aligned patterning method by using non-conformal film and etch...
- Patent number 7,943,980
- Issue date May 17, 2011
- Spansion LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned patterning method by using non-conformal film and etch...
- Patent number 7,906,395
- Issue date Mar 15, 2011
- Spansion LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using thick spacer for bitline implant then remove
- Patent number 7,888,218
- Issue date Feb 15, 2011
- Spansion LLC
- Zhizheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned patterning method by using non-conformal film and etch...
- Patent number 7,803,680
- Issue date Sep 28, 2010
- Spansion LLC
- Shenging Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual storage node memory devices and methods for fabricating the same
- Patent number 7,785,965
- Issue date Aug 31, 2010
- Spansion LLC
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory comprising dual charge storage nodes and metho...
- Patent number 7,767,517
- Issue date Aug 3, 2010
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective application of word line bias to minimize fringe effects...
- Patent number 7,746,705
- Issue date Jun 29, 2010
- Spansion LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for fabricating flash memory devices
- Patent number 7,696,038
- Issue date Apr 13, 2010
- Spansion LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Deep bitline implant to avoid program disturb
- Patent number 7,671,405
- Issue date Mar 2, 2010
- Spansion LLC
- Timothy Thurgate
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-phase wordline erasing for flash memory
- Patent number 7,626,869
- Issue date Dec 1, 2009
- Spansion LLC
- Xuguang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduction of leakage current and program disturbs in flash memory d...
- Patent number 7,489,560
- Issue date Feb 10, 2009
- Spansion LLC
- Kuo-Tung Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of increasing erase speed in memory arrays
- Patent number 7,462,907
- Issue date Dec 9, 2008
- Spansion LLC
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TILTED IMPLANT FOR POLY RESISTORS
- Publication number 20190385853
- Publication date Dec 19, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHARGE-TRAPPING MEMORY DEVICE
- Publication number 20160126250
- Publication date May 5, 2016
- SPANSION LLC
- Kuo Tung Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TILTED IMPLANT FOR POLY RESISTORS
- Publication number 20150333188
- Publication date Nov 19, 2015
- SPANSION LLC
- Shenqing FANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FORMING EDGE WORDLINE IMPLANTS ADJACENT EDGE WORDLINES
- Publication number 20150171100
- Publication date Jun 18, 2015
- SPANSION LLC
- Timothy THURGATE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE
- Publication number 20150155285
- Publication date Jun 4, 2015
- Micron Technology, Inc.
- Srinivasa R. BANNA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY
- Publication number 20140312409
- Publication date Oct 23, 2014
- SPANSION LLC
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE
- Publication number 20140029360
- Publication date Jan 30, 2014
- Micron Technology, Inc.
- Srinivasa R. BANNA
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE
- Publication number 20140003144
- Publication date Jan 2, 2014
- Micron Technology, Inc.
- Srinivasa R. BANNA
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR ROUNDED ONO FORMATION IN A FLASH MEMORY DE...
- Publication number 20140001534
- Publication date Jan 2, 2014
- Shenqing FANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE PROTECTION LAYER
- Publication number 20130228851
- Publication date Sep 5, 2013
- SPANSION LLC
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE
- Publication number 20120307568
- Publication date Dec 6, 2012
- Micron Technology, Inc.
- Srinivasa Rao Banna
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE
- Publication number 20120294083
- Publication date Nov 22, 2012
- Micron Technology, Inc.
- Srinivasa Rao Banna
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE
- Publication number 20110222356
- Publication date Sep 15, 2011
- Innovative Silicon Isi SA
- Srinivasa Rao Banna
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH...
- Publication number 20110013449
- Publication date Jan 20, 2011
- Shenqing FANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH...
- Publication number 20110012191
- Publication date Jan 20, 2011
- Shenqing FANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...
- Publication number 20100283100
- Publication date Nov 11, 2010
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS...
- Publication number 20100208527
- Publication date Aug 19, 2010
- SPANSION LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE S...
- Publication number 20090256242
- Publication date Oct 15, 2009
- SPANSION LLC
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selective Application Of Word Line Bias To Minimize Fringe Effects...
- Publication number 20090147589
- Publication date Jun 11, 2009
- SPANSION LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY
- Publication number 20080279014
- Publication date Nov 13, 2008
- SPANSION LLC
- Xuguang Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Self-aligned patterning method by using non-conformal film and etch...
- Publication number 20080171416
- Publication date Jul 17, 2008
- Shenging Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Using thick spacer for bitline implant then remove
- Publication number 20080153223
- Publication date Jun 26, 2008
- Spansion LLC
- Zhizheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...
- Publication number 20080149999
- Publication date Jun 26, 2008
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Deep bitline implant to avoid program disturb
- Publication number 20080153274
- Publication date Jun 26, 2008
- Timothy Thurgate
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE PROTECTION LAYER
- Publication number 20080135913
- Publication date Jun 12, 2008
- SPANSION LLC
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL STORAGE NODE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
- Publication number 20080064165
- Publication date Mar 13, 2008
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reduction of leakage current and program disturbs in flash memory d...
- Publication number 20070247907
- Publication date Oct 25, 2007
- Kuo-Tung Chang
- G11 - INFORMATION STORAGE
Information Patent Application
Structure and method for low Vss resistance and reduced dibl in a f...
- Publication number 20050164450
- Publication date Jul 28, 2005
- FASL, LLC, a limited liability company
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cell array with staggered local inter-connect structure
- Publication number 20050077567
- Publication date Apr 14, 2005
- Mark W. Randolph
- G11 - INFORMATION STORAGE
Information Patent Application
Lateral doped channel
- Publication number 20040102026
- Publication date May 27, 2004
- Nga-Ching Wong
- H01 - BASIC ELECTRIC ELEMENTS

Timothy James Thurgate

Person

Patents Grantslast 30 patents

Tilted implant for poly resistors

Charge-trapping memory device

Apparatus and method for rounded ONO formation in a flash memory de...

Semiconductor memory device and method for biasing same

Techniques for providing a semiconductor memory device

Process for forming edge wordline implants adjacent edge wordlines

System and method for manufacturing self-aligned STI with single poly

Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device

Self-aligned STI with single poly for manufacturing a flash memory...

Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device

Memory device protection layer

Method of forming an electronic device including forming a charge s...

Apparatus and method for extended nitride layer in a flash memory

Memory device with buried bit line structure

Semiconductor memory comprising dual charge storage nodes and metho...

Selective application of word line bias to minimize fringe effects...

Self-aligned patterning method by using non-conformal film and etch...

Self-aligned patterning method by using non-conformal film and etch...

Using thick spacer for bitline implant then remove

Self-aligned patterning method by using non-conformal film and etch...

Dual storage node memory devices and methods for fabricating the same

Semiconductor memory comprising dual charge storage nodes and metho...

Selective application of word line bias to minimize fringe effects...

Methods for fabricating flash memory devices

Deep bitline implant to avoid program disturb

Multi-phase wordline erasing for flash memory

Reduction of leakage current and program disturbs in flash memory d...

Method of increasing erase speed in memory arrays

Patents Applicationslast 30 patents

TILTED IMPLANT FOR POLY RESISTORS

CHARGE-TRAPPING MEMORY DEVICE

TILTED IMPLANT FOR POLY RESISTORS

PROCESS FOR FORMING EDGE WORDLINE IMPLANTS ADJACENT EDGE WORDLINES

TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE

SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY

TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE

TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE

APPARATUS AND METHOD FOR ROUNDED ONO FORMATION IN A FLASH MEMORY DE...

MEMORY DEVICE PROTECTION LAYER

TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE

TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE

TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE

SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH...

SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH...

SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...

SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS...

METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE S...

Selective Application Of Word Line Bias To Minimize Fringe Effects...

MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY

Self-aligned patterning method by using non-conformal film and etch...

Using thick spacer for bitline implant then remove

SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...

Deep bitline implant to avoid program disturb

MEMORY DEVICE PROTECTION LAYER

DUAL STORAGE NODE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

Reduction of leakage current and program disturbs in flash memory d...

Structure and method for low Vss resistance and reduced dibl in a f...

Memory cell array with staggered local inter-connect structure

Lateral doped channel