Todd Edwin Leonard

Person

Williston, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Aligning FIFO pointers in a data communications lane of a serial link
- Patent number 9,600,232
- Issue date Mar 21, 2017
- International Business Machines Corporation
- John J. Bergkvist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional inter-chip contact through vertical displacement...
- Patent number 9,337,173
- Issue date May 10, 2016
- International Business Machines Corporation
- Kenneth J. Goodnow
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Three-dimensional chip stack for self-powered integrated circuit
- Patent number 9,230,940
- Issue date Jan 5, 2016
- GLOBALFOUNDRIES Inc.
- Kenneth J. Goodnow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional inter-chip contact through vertical displacement...
- Patent number 9,123,492
- Issue date Sep 1, 2015
- International Business Machines Corporation
- Kenneth J. Goodnow
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Adaptable receiver detection
- Patent number 8,989,313
- Issue date Mar 24, 2015
- International Business Machines Corporation
- John J. Bergkvist
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Environmental and computing cost reduction with improved reliabilit...
- Patent number 8,793,365
- Issue date Jul 29, 2014
- International Business Machines Corporation
- Igor Arsovski
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Source series terminated driver circuit with programmable output re...
- Patent number 8,618,833
- Issue date Dec 31, 2013
- International Business Machines Corporation
- John J. Bergkvist
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Warranty monitoring and enforcement for integrated circuit and rela...
- Patent number 8,452,566
- Issue date May 28, 2013
- International Business Machines Corporation
- Kenneth J. Goodnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for improving equalization in a high speed serdes...
- Patent number 8,396,106
- Issue date Mar 12, 2013
- International Business Machines Corporation
- Brian J. Connolly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Structure for hardware assisted bus state transition circuit using...
- Patent number 8,347,019
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip identification circuit incorporating pairs of conductors, e...
- Patent number 8,291,357
- Issue date Oct 16, 2012
- International Business Machines Corporation
- Serafino Bueti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for pipelined cyclic redundancy check circuit with multip...
- Patent number 8,136,010
- Issue date Mar 13, 2012
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic critical path detector for digital logic circuit paths
- Patent number 8,132,136
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and systems of powering on integrated circuit
- Patent number 8,016,482
- Issue date Sep 13, 2011
- International Business Machines Corporation
- Igor Arsovski
- G05 - CONTROLLING REGULATING
Information Patent Grant
Dynamic critical path detector for digital logic circuit paths
- Patent number 7,941,772
- Issue date May 10, 2011
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Grant
System-on-chip (SOC), design structure and method
- Patent number 7,904,872
- Issue date Mar 8, 2011
- International Business Machines Corporation
- Jonathan P. Ebbers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip (SOC), design structure and method
- Patent number 7,904,873
- Issue date Mar 8, 2011
- International Business Machines Corporation
- Jonathan P. Ebbers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Critical path redundant logic for mitigation of hardware across chi...
- Patent number 7,898,286
- Issue date Mar 1, 2011
- International Business Machines Corporation
- Igor Arsovski
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for pipelined cyclic redundancy check circuit with multip...
- Patent number 7,886,210
- Issue date Feb 8, 2011
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for monitoring channel eye characteristics in a high-speed S...
- Patent number 7,869,379
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Brian J. Connolly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Structure for task based debugger (transaction-event-job-trigger)
- Patent number 7,823,017
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for monitoring BER in an infiniband environment
- Patent number 7,715,323
- Issue date May 11, 2010
- International Business Machines Corporation
- Brian J. Connolly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Design structures of powering on integrated circuit
- Patent number 7,716,007
- Issue date May 11, 2010
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Task based debugger (transaction-event-job-trigger)
- Patent number 7,594,140
- Issue date Sep 22, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for transmitting data in an integrated circuit
- Patent number 7,571,377
- Issue date Aug 4, 2009
- International Business Machines Corporation
- Brian John Connolly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Design structures, method and systems of powering on integrated cir...
- Patent number 7,483,806
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel parallel CRC generation and checking circuit
- Patent number 7,225,387
- Issue date May 29, 2007
- International Business Machines Corporation
- Ming-i M. Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scalable cyclic redundancy check circuit
- Patent number 7,103,832
- Issue date Sep 5, 2006
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Communications adapter for implementing communications in a network...
- Patent number 6,765,911
- Issue date Jul 20, 2004
- International Business Machines Corporation
- Mark William Branstad
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Communications methods and gigabit ethernet communications adapter...
- Patent number 6,498,782
- Issue date Dec 24, 2002
- International Business Machines Corporation
- Mark William Branstad
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL INTER-CHIP CONTACT THROUGH VERTICAL DISPLACEMENT...
- Publication number 20150348947
- Publication date Dec 3, 2015
- International Business Machines Corporation
- Kenneth J. GOODNOW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALIGNING FIFO POINTERS IN A DATA COMMUNICATIONS LANE OF A SERIAL LINK
- Publication number 20150160920
- Publication date Jun 11, 2015
- International Business Machines Corporation
- John J. Bergkvist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL CHIP STACK FOR SELF-POWERED INTEGRATED CIRCUIT
- Publication number 20150077173
- Publication date Mar 19, 2015
- International Business Machines Corporation
- Kenneth J. GOODNOW
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
ADAPTABLE RECEIVER DETECTION
- Publication number 20140254650
- Publication date Sep 11, 2014
- International Business Machines Corporation
- John J. Bergkvist
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
THREE-DIMENSIONAL INTER-CHIP CONTACT THROUGH VERTICAL DISPLACEMENT...
- Publication number 20140166461
- Publication date Jun 19, 2014
- International Business Machines Corporation
- Kenneth J. Goodnow
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SOURCE SERIES TERMINATED DRIVER CIRCUIT WITH PROGRAMMABLE OUTPUT RE...
- Publication number 20130335120
- Publication date Dec 19, 2013
- International Business Machines Corporation
- John J. Bergkvist
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ENVIRONMENTAL AND COMPUTING COST REDUCTION WITH IMPROVED RELIABILIT...
- Publication number 20100228861
- Publication date Sep 9, 2010
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Critical Path Redundant Logic for Mitigation of Hardware Across Chi...
- Publication number 20100201377
- Publication date Aug 12, 2010
- International Business Machines Corporation
- Igor ARSOVSKI
- G01 - MEASURING TESTING
Information Patent Application
DESIGN STRUCTURE FOR AUTOMATED MEANS FOR DETERMINING INTERNET ACCES...
- Publication number 20100011138
- Publication date Jan 14, 2010
- International Business Machines Corporation
- Jonathan Phillip Ebbers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System-On-Chip (SOC), Design Structure and Method
- Publication number 20090291533
- Publication date Nov 26, 2009
- Jonathan P. Ebbers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System-On-Chip (SOC), Design Structure and Method
- Publication number 20090292828
- Publication date Nov 26, 2009
- Jonathan P. Ebbers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WARRANTY MONITORING AND ENFORCEMENT FOR INTEGRATED CIRCUIT AND RELA...
- Publication number 20090276178
- Publication date Nov 5, 2009
- Kenneth J. Goodnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WARRANTY MONITORING AND ENFORCEMENT FOR INTEGRATED CIRCUIT
- Publication number 20090276232
- Publication date Nov 5, 2009
- Kenneth J. Goodnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES...
- Publication number 20090257514
- Publication date Oct 15, 2009
- Brian J. Connolly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES...
- Publication number 20090245110
- Publication date Oct 1, 2009
- Brian J. Connolly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIP...
- Publication number 20090164865
- Publication date Jun 25, 2009
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN IN...
- Publication number 20090132732
- Publication date May 21, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRON...
- Publication number 20090132747
- Publication date May 21, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM
- Publication number 20090094566
- Publication date Apr 9, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP IDENTIFICATION SYSTEM AND METHOD
- Publication number 20090091351
- Publication date Apr 9, 2009
- Serafino Bueti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
- Publication number 20090044160
- Publication date Feb 12, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
- Publication number 20090044054
- Publication date Feb 12, 2009
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURES OF POWERING ON INTEGRATED CIRCUIT
- Publication number 20090024972
- Publication date Jan 22, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT
- Publication number 20090022203
- Publication date Jan 22, 2009
- Igor Arsovski
- G05 - CONTROLLING REGULATING
Information Patent Application
DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIR...
- Publication number 20090021085
- Publication date Jan 22, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MONITORING CHANNEL EYE CHARACTERISTICS IN A HIGH-SPEED S...
- Publication number 20080285443
- Publication date Nov 20, 2008
- International Business Machines Corporation
- Brian J. Connolly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD FOR MONITORING BER IN AN INFINIBAND ENVIRONMENT
- Publication number 20080285453
- Publication date Nov 20, 2008
- International Business Machines Corporation
- Brian J. Connolly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND PROCESSING UNIT FOR INTER-CHIP COMMUNICATION
- Publication number 20080282005
- Publication date Nov 13, 2008
- Edward Chencinski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT...
- Publication number 20080282015
- Publication date Nov 13, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Executing Software Within Real-Time Hardware Constraints Using Func...
- Publication number 20080282072
- Publication date Nov 13, 2008
- Todd E. Leonard
- G06 - COMPUTING CALCULATING COUNTING

Todd Edwin Leonard

Person

Patents Grantslast 30 patents

Aligning FIFO pointers in a data communications lane of a serial link

Three-dimensional inter-chip contact through vertical displacement...

Three-dimensional chip stack for self-powered integrated circuit

Three-dimensional inter-chip contact through vertical displacement...

Adaptable receiver detection

Environmental and computing cost reduction with improved reliabilit...

Source series terminated driver circuit with programmable output re...

Warranty monitoring and enforcement for integrated circuit and rela...

System and method for improving equalization in a high speed serdes...

Structure for hardware assisted bus state transition circuit using...

On-chip identification circuit incorporating pairs of conductors, e...

Apparatus for pipelined cyclic redundancy check circuit with multip...

Dynamic critical path detector for digital logic circuit paths

Method and systems of powering on integrated circuit

Dynamic critical path detector for digital logic circuit paths

System-on-chip (SOC), design structure and method

System-on-chip (SOC), design structure and method

Critical path redundant logic for mitigation of hardware across chi...

Apparatus for pipelined cyclic redundancy check circuit with multip...

Method for monitoring channel eye characteristics in a high-speed S...

Structure for task based debugger (transaction-event-job-trigger)

Method for monitoring BER in an infiniband environment

Design structures of powering on integrated circuit

Task based debugger (transaction-event-job-trigger)

Method and apparatus for transmitting data in an integrated circuit

Design structures, method and systems of powering on integrated cir...

Multilevel parallel CRC generation and checking circuit

Scalable cyclic redundancy check circuit

Communications adapter for implementing communications in a network...

Communications methods and gigabit ethernet communications adapter...

Patents Applicationslast 30 patents

THREE-DIMENSIONAL INTER-CHIP CONTACT THROUGH VERTICAL DISPLACEMENT...

ALIGNING FIFO POINTERS IN A DATA COMMUNICATIONS LANE OF A SERIAL LINK

THREE-DIMENSIONAL CHIP STACK FOR SELF-POWERED INTEGRATED CIRCUIT

ADAPTABLE RECEIVER DETECTION

THREE-DIMENSIONAL INTER-CHIP CONTACT THROUGH VERTICAL DISPLACEMENT...

SOURCE SERIES TERMINATED DRIVER CIRCUIT WITH PROGRAMMABLE OUTPUT RE...

ENVIRONMENTAL AND COMPUTING COST REDUCTION WITH IMPROVED RELIABILIT...

Critical Path Redundant Logic for Mitigation of Hardware Across Chi...

DESIGN STRUCTURE FOR AUTOMATED MEANS FOR DETERMINING INTERNET ACCES...

System-On-Chip (SOC), Design Structure and Method

System-On-Chip (SOC), Design Structure and Method

WARRANTY MONITORING AND ENFORCEMENT FOR INTEGRATED CIRCUIT AND RELA...

WARRANTY MONITORING AND ENFORCEMENT FOR INTEGRATED CIRCUIT

SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES...

SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES...

APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIP...

UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN IN...

STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRON...

DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM

CHIP IDENTIFICATION SYSTEM AND METHOD

DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS

DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS

STRUCTURES OF POWERING ON INTEGRATED CIRCUIT

METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT

DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIR...

METHOD FOR MONITORING CHANNEL EYE CHARACTERISTICS IN A HIGH-SPEED S...

METHOD FOR MONITORING BER IN AN INFINIBAND ENVIRONMENT

METHOD AND PROCESSING UNIT FOR INTER-CHIP COMMUNICATION

DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT...

Executing Software Within Real-Time Hardware Constraints Using Func...