Tsu-Wei Ku

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Chip-area reduction and congestion alleviation by timing-and-routab...
- Patent number 7,200,827
- Issue date Apr 3, 2007
- Apex Design Systems, Inc.
- Tsu-Wei Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus of relative datapath cell placement with struc...
- Patent number 6,792,585
- Issue date Sep 14, 2004
- Arcadia Design Systems, Inc.
- Tsu-Wei Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for mixed placement of structured and non-structured circuit...
- Patent number 5,930,499
- Issue date Jul 27, 1999
- Arcadia Design Systems, Inc.
- Yulin Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuit simulator and logic simulation method having reduced...
- Patent number 5,384,720
- Issue date Jan 24, 1995
- Hitachi Micro Systems Inc.
- Tsu-Wei Ku
- G06 - COMPUTING CALCULATING COUNTING