Tu Tam VU

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer-level packaging using wire bond wires in place of a redistrib...
- Patent number 10,008,469
- Issue date Jun 26, 2018
- Invensas Corporation
- Rajesh Katkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flipped die stacks with multiple rows of leadframe interconnects
- Patent number 9,859,257
- Issue date Jan 2, 2018
- Invensas Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out wafer-level packaging using metal foil lamination
- Patent number 9,847,238
- Issue date Dec 19, 2017
- Invensas Corporation
- Xuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out wafer-level packaging using metal foil lamination
- Patent number 9,646,946
- Issue date May 9, 2017
- Invensas Corporation
- Xuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level packages with mechanically decoupled fan-in and fan-out...
- Patent number 9,543,277
- Issue date Jan 10, 2017
- Invensas Corporation
- Bongsub Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flipped die stacks with multiple rows of leadframe interconnects
- Patent number 9,508,691
- Issue date Nov 29, 2016
- Invensas Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level packaging using wire bond wires in place of a redistrib...
- Patent number 9,502,372
- Issue date Nov 22, 2016
- Invensas Corporation
- Rajesh Katkar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FLIPPED DIE STACKS WITH MULTIPLE ROWS OF LEADFRAME INTERCONNECTS
- Publication number 20170179081
- Publication date Jun 22, 2017
- Invensas Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-Out Wafer-Level Packaging Using Metal Foil Lamination
- Publication number 20170170031
- Publication date Jun 15, 2017
- Invensas Corporation
- Xuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAN-OUT WAFER-LEVEL PACKAGING USING METAL FOIL LAMINATION
- Publication number 20170103957
- Publication date Apr 13, 2017
- Invensas Corporation
- Xuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIB...
- Publication number 20170069591
- Publication date Mar 9, 2017
- Invensas Corporation
- Rajesh KATKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIB...
- Publication number 20160322326
- Publication date Nov 3, 2016
- Invensas Corporation
- Rajesh KATKAR
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Wafer-level packaging using wire bond wires in place of a redistrib...

Flipped die stacks with multiple rows of leadframe interconnects

Fan-out wafer-level packaging using metal foil lamination

Fan-out wafer-level packaging using metal foil lamination

Wafer level packages with mechanically decoupled fan-in and fan-out...

Flipped die stacks with multiple rows of leadframe interconnects

Wafer-level packaging using wire bond wires in place of a redistrib...

Patents Applicationslast 30 patents

FLIPPED DIE STACKS WITH MULTIPLE ROWS OF LEADFRAME INTERCONNECTS

Fan-Out Wafer-Level Packaging Using Metal Foil Lamination

FAN-OUT WAFER-LEVEL PACKAGING USING METAL FOIL LAMINATION

WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIB...

WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIB...