Vasisht M. Vadi

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Digital signal processing block with preadder stage
- Patent number 8,543,635
- Issue date Sep 24, 2013
- Xilinx, Inc.
- James M. Simkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Determining timing paths within a circuit block of a programmable i...
- Patent number 8,117,577
- Issue date Feb 14, 2012
- Xilinx, Inc.
- Vasisht M. Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline FFT architecture for a programmable device
- Patent number 8,001,171
- Issue date Aug 16, 2011
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processing element having an arithmetic logic unit
- Patent number 7,882,165
- Issue date Feb 1, 2011
- Xilinx, Inc.
- James M. Simkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit having an adder circuit with carr...
- Patent number 7,870,182
- Issue date Jan 11, 2011
- Xilinx Inc.
- John M. Thendean
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing block having a wide multiplexer
- Patent number 7,865,542
- Issue date Jan 4, 2011
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit having a pattern circuit for dete...
- Patent number 7,860,915
- Issue date Dec 28, 2010
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit having a SIMD circuit
- Patent number 7,853,634
- Issue date Dec 14, 2010
- Xilinx, Inc.
- James M. Simkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit having a pattern detector circuit...
- Patent number 7,853,636
- Issue date Dec 14, 2010
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architectural floorplan for a digital signal processing circuit
- Patent number 7,853,632
- Issue date Dec 14, 2010
- Xilinx, Inc.
- Alvin Y. Ching
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit having a pattern detector circuit
- Patent number 7,849,119
- Issue date Dec 7, 2010
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit having a pre-adder circuit
- Patent number 7,844,653
- Issue date Nov 30, 2010
- Xilinx, Inc.
- James M. Simkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal processing circuit having input register blocks
- Patent number 7,840,627
- Issue date Nov 23, 2010
- Xilinx, Inc.
- James M. Simkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Arithmetic logic unit circuit
- Patent number 7,840,630
- Issue date Nov 23, 2010
- Xilinx, Inc.
- Anna Wing Wah Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit having embedded differential clock tree
- Patent number 7,759,973
- Issue date Jul 20, 2010
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,518,401
- Issue date Apr 14, 2009
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device having an embedded differential clock tree
- Patent number 7,414,430
- Issue date Aug 19, 2008
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustable global tap voltage to improve memory cell yield
- Patent number 7,394,708
- Issue date Jul 1, 2008
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,372,299
- Issue date May 13, 2008
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for configuring an integrated circuit
- Patent number 7,314,174
- Issue date Jan 1, 2008
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Segmented dataline scheme in a memory with enhanced full fault cove...
- Patent number 7,286,382
- Issue date Oct 23, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G11 - INFORMATION STORAGE
Information Patent Grant
Data monitoring for single event upset in a programmable logic device
- Patent number 7,283,409
- Issue date Oct 16, 2007
- Xilinx, Inc.
- Martin L. Voogel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfiguration port for dynamic reconfiguration-system monitor int...
- Patent number 7,233,532
- Issue date Jun 19, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bidirectional register segmented data busing
- Patent number 7,233,169
- Issue date Jun 19, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G11 - INFORMATION STORAGE
Information Patent Grant
Reconfiguration port for dynamic reconfiguration
- Patent number 7,218,137
- Issue date May 15, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for a multiplexed address line driver
- Patent number 7,196,940
- Issue date Mar 27, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed configurable transceiver architecture
- Patent number 7,187,709
- Issue date Mar 6, 2007
- Xilinx, Inc.
- Suresh M. Menon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Segmented dataline scheme in a memory with enhanced full fault cove...
- Patent number 7,142,442
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient implementation of a bypassable flip-flop with a clock enable
- Patent number 7,129,762
- Issue date Oct 31, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,129,765
- Issue date Oct 31, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE
- Publication number 20100191786
- Publication date Jul 29, 2010
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20070013428
- Publication date Jan 18, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20060290403
- Publication date Dec 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device having an embedded differential clock tree
- Publication number 20060290402
- Publication date Dec 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing circuit having a pattern circuit for dete...
- Publication number 20060288070
- Publication date Dec 21, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing circuit having a SIMD circuit
- Publication number 20060288069
- Publication date Dec 21, 2006
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architectural floorplan for a digital signal processing circuit
- Publication number 20060230092
- Publication date Oct 12, 2006
- Xilinx, Inc.
- Alvin Y. Ching
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing circuit having a pre-adder circuit
- Publication number 20060230095
- Publication date Oct 12, 2006
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing circuit having a pattern detector circuit...
- Publication number 20060230093
- Publication date Oct 12, 2006
- Xilinx, Inc.
- Bernard J. New
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing circuit having an adder circuit with carr...
- Publication number 20060230096
- Publication date Oct 12, 2006
- Xilinx, Inc.
- John M. Thendean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing circuit having input register blocks
- Publication number 20060230094
- Publication date Oct 12, 2006
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing block having a wide multiplexer
- Publication number 20060212499
- Publication date Sep 21, 2006
- Xilinx, Inc.
- Bernard J. New
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Arithmetic logic unit circuit
- Publication number 20060206557
- Publication date Sep 14, 2006
- Xilinx, Inc.
- Anna Wing Wah Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing circuit having a pattern detector circuit
- Publication number 20060195496
- Publication date Aug 31, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processing element having an arithmetic logic unit
- Publication number 20060190516
- Publication date Aug 24, 2006
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reconfiguration port for dynamic reconfiguration
- Publication number 20050248364
- Publication date Nov 10, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20050242865
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reconfiguration port for dynamic reconfiguration - sub-frame access...
- Publication number 20050242834
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reconfiguration port for dynamic reconfiguration-system monitor int...
- Publication number 20050246520
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reconfiguration port for dynamic reconfiguration-controller
- Publication number 20050242835
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device having an embedded differential clock tree
- Publication number 20050242866
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING

Vasisht M. Vadi

Person

Patents Grantslast 30 patents

Digital signal processing block with preadder stage

Determining timing paths within a circuit block of a programmable i...

Pipeline FFT architecture for a programmable device

Digital signal processing element having an arithmetic logic unit

Digital signal processing circuit having an adder circuit with carr...

Digital signal processing block having a wide multiplexer

Digital signal processing circuit having a pattern circuit for dete...

Digital signal processing circuit having a SIMD circuit

Digital signal processing circuit having a pattern detector circuit...

Architectural floorplan for a digital signal processing circuit

Digital signal processing circuit having a pattern detector circuit

Digital signal processing circuit having a pre-adder circuit

Digital signal processing circuit having input register blocks

Arithmetic logic unit circuit

Integrated circuit having embedded differential clock tree

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Adjustable global tap voltage to improve memory cell yield

Differential clock tree in an integrated circuit

Method and system for configuring an integrated circuit

Segmented dataline scheme in a memory with enhanced full fault cove...

Data monitoring for single event upset in a programmable logic device

Reconfiguration port for dynamic reconfiguration-system monitor int...

Bidirectional register segmented data busing

Reconfiguration port for dynamic reconfiguration

Method and apparatus for a multiplexed address line driver

High speed configurable transceiver architecture

Segmented dataline scheme in a memory with enhanced full fault cove...

Efficient implementation of a bypassable flip-flop with a clock enable

Differential clock tree in an integrated circuit

Patents Applicationslast 30 patents

DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE

Differential clock tree in an integrated circuit

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Digital signal processing circuit having a pattern circuit for dete...

Digital signal processing circuit having a SIMD circuit

Architectural floorplan for a digital signal processing circuit

Digital signal processing circuit having a pre-adder circuit

Digital signal processing circuit having a pattern detector circuit...

Digital signal processing circuit having an adder circuit with carr...

Digital signal processing circuit having input register blocks

Digital signal processing block having a wide multiplexer

Arithmetic logic unit circuit

Digital signal processing circuit having a pattern detector circuit

Digital signal processing element having an arithmetic logic unit

Reconfiguration port for dynamic reconfiguration

Differential clock tree in an integrated circuit

Reconfiguration port for dynamic reconfiguration - sub-frame access...

Reconfiguration port for dynamic reconfiguration-system monitor int...

Reconfiguration port for dynamic reconfiguration-controller

Programmable logic device having an embedded differential clock tree