Vinod Robert Purayath

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Three-dimensional memory structure fabrication using channel replac...
- Patent number 12,205,645
- Issue date Jan 21, 2025
- SUNRISE MEMORY CORPORATION
- Shohei Kamisaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional memory string array of thin-film ferroelectric tr...
- Patent number 12,160,996
- Issue date Dec 3, 2024
- SUNRISE MEMORY CORPORATION
- Christopher J. Petti
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for a 3-dimensional array of horizontal nor-type memory str...
- Patent number 11,917,821
- Issue date Feb 27, 2024
- SUNRISE MEMORY CORPORATION
- Vinod Purayath
Information Patent Grant
Process for preparing a channel region of a thin-film transistor in...
- Patent number 11,844,204
- Issue date Dec 12, 2023
- SUNRISE MEMORY CORPORATION
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3-dimensional memory string array of thin-film ferroelectric transi...
- Patent number 11,839,086
- Issue date Dec 5, 2023
- SUNRISE MEMORY CORPORATION
- Christopher J. Petti
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for fabricating a 3-dimensional memory structure of nor mem...
- Patent number 11,751,391
- Issue date Sep 5, 2023
- SUNRISE MEMORY CORPORATION
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for preparing a channel region of a thin-film transistor in...
- Patent number 11,515,309
- Issue date Nov 29, 2022
- SUNRISE MEMORY CORPORATION
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for a 3-dimensional array of horizontal NOR-type memory str...
- Patent number 11,217,600
- Issue date Jan 4, 2022
- SUNRISE MEMORY CORPORATION
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for three-dimensional NAND structure fabrication
- Patent number 10,790,298
- Issue date Sep 29, 2020
- Applied Materials, Inc.
- Vinod Robert Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D flash memory cells which discourage cross-cell electrical tunneling
- Patent number 10,541,246
- Issue date Jan 21, 2020
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Accommodating imperfectly aligned memory holes
- Patent number 10,529,737
- Issue date Jan 7, 2020
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge-trap layer separation and word-line isolation in a 3-D NAND...
- Patent number 10,468,259
- Issue date Nov 5, 2019
- Applied Materials, Inc.
- Vinod Robert Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Accommodating imperfectly aligned memory holes
- Patent number 10,325,923
- Issue date Jun 18, 2019
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Accommodating imperfectly aligned memory holes
- Patent number 10,319,739
- Issue date Jun 11, 2019
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge-trap layer separation and word-line isolation for enhanced 3...
- Patent number 9,960,045
- Issue date May 1, 2018
- Applied Materials, Inc.
- Vinod Robert Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated bit-line airgap formation and gate stack post clean
- Patent number 9,773,695
- Issue date Sep 26, 2017
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory with flat cell structures and air gap isolation
- Patent number 9,698,149
- Issue date Jul 4, 2017
- SanDisk Technologies LLC
- Vinod Robert Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench vertical NAND and method of making thereof
- Patent number 9,552,991
- Issue date Jan 24, 2017
- SanDisk Technologies LLC
- Akira Matsudaira
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile storage element with suspended charge storage region
- Patent number 9,548,311
- Issue date Jan 17, 2017
- SanDisk Technologies LLC
- Donovan Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated bit-line airgap formation and gate stack post clean
- Patent number 9,496,167
- Issue date Nov 15, 2016
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistance-switching memory cell with multiple raised structures in...
- Patent number 9,466,644
- Issue date Oct 11, 2016
- SanDisk Technologies LLC
- George Matamis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Air gap isolation in non-volatile memory
- Patent number 9,460,958
- Issue date Oct 4, 2016
- SanDisk Technologies LLC
- Vinod R Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical gate separation
- Patent number 9,449,846
- Issue date Sep 20, 2016
- Applied Materials, Inc.
- Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming resistance-switching memory cell with multiple e...
- Patent number 9,437,813
- Issue date Sep 6, 2016
- SanDisk Technologies LLC
- George Matamis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Air gaps between copper lines
- Patent number 9,396,989
- Issue date Jul 19, 2016
- Applied Materials, Inc.
- Vinod R. Purayath
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Metal control gate structures and air gap isolation in non-volatile...
- Patent number 9,379,120
- Issue date Jun 28, 2016
- SanDisk Technologies Inc.
- Vinod Robert Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated oxide recess and floating gate fin trimming
- Patent number 9,378,978
- Issue date Jun 28, 2016
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile storage element with suspended charge storage region
- Patent number 9,349,740
- Issue date May 24, 2016
- SanDisk Technologies Inc.
- Donovan Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanodot enhanced hybrid floating gate for non-volatile memory devices
- Patent number 9,331,181
- Issue date May 3, 2016
- SanDisk Technologies Inc.
- Donovan Lee
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Dopant etch selectivity control
- Patent number 9,263,278
- Issue date Feb 16, 2016
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TR...
- Publication number 20250113493
- Publication date Apr 3, 2025
- Sunrise Memory Corporation
- Christopher J. Petti
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TR...
- Publication number 20240040798
- Publication date Feb 1, 2024
- Sunrise Memory Corporation
- Christopher J. Petti
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR FABRICATING A 3-DIMENSIONAL MEMORY STRUCTURE OF NOR MEM...
- Publication number 20230247831
- Publication date Aug 3, 2023
- Sunrise Memory Corporation
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STR...
- Publication number 20230157019
- Publication date May 18, 2023
- SUNRISE MEMORY CORPORATION
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR PREPARING A CHANNEL REGION OF A THIN-FILM TRANSISTOR IN...
- Publication number 20230072345
- Publication date Mar 9, 2023
- Sunrise Memory Corporation
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSI...
- Publication number 20230027837
- Publication date Jan 26, 2023
- Sunrise Memory Corporation
- Christopher J. Petti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY STRUCTURE FABRICATED USING REPEATED ACTIVE...
- Publication number 20220383953
- Publication date Dec 1, 2022
- Sunrise Memory Corporation
- Shohei Kamisaka
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR FABRICATION OF 3-DIMENSIONAL NOR MEMORY ARRAYS
- Publication number 20220344364
- Publication date Oct 27, 2022
- Sunrise Memory Corporation
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY STRUCTURE FABRICATION USING CHANNEL REPLAC...
- Publication number 20220343980
- Publication date Oct 27, 2022
- Sunrise Memory Corporation
- Shohei Kamisaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL NOR FLASH THIN FILM TRANSISTOR STRINGS AND FABRICATION THE...
- Publication number 20220231040
- Publication date Jul 21, 2022
- Sunrise Memory Corporation
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN-FILM STORAGE TRANSISTOR WITH FERROELECTRIC STORAGE LAYER
- Publication number 20220173251
- Publication date Jun 2, 2022
- Sunrise Memory Corporation
- George Samachisa
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR FABRICATING A 3-DIMENSIONAL MEMORY STRUCTURE OF NOR MEM...
- Publication number 20220028886
- Publication date Jan 27, 2022
- Sunrise Memory Corporation
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING A 3-DIMENSIONAL MEMORY STRUCTURE OF NOR MEM...
- Publication number 20220028876
- Publication date Jan 27, 2022
- Sunrise Memory Corporation
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR PREPARING A CHANNEL REGION OF A THIN-FILM TRANSISTOR IN...
- Publication number 20210193660
- Publication date Jun 24, 2021
- SUNRISE MEMORY CORPORATION
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STR...
- Publication number 20210013224
- Publication date Jan 14, 2021
- SUNRISE MEMORY CORPORATION
- Vinod Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR THREE-DIMENSIONAL NAND STRUCTURE FABRICATION
- Publication number 20200227433
- Publication date Jul 16, 2020
- Applied Materials, Inc.
- VINOD ROBERT PURAYATH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE IMPROVEMENT
- Publication number 20200051994
- Publication date Feb 13, 2020
- Applied Materials, Inc.
- Vinod Robert PURAYATH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES
- Publication number 20190296045
- Publication date Sep 26, 2019
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D FLASH MEMORY CELLS WHICH DISCOURAGE CROSS-CELL ELECTRICAL TUNNELING
- Publication number 20180374863
- Publication date Dec 27, 2018
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHARGE-TRAP LAYER SEPARATION AND WORD-LINE ISOLATION IN A 3-D NAND...
- Publication number 20180254187
- Publication date Sep 6, 2018
- Applied Materials, Inc.
- Vinod Robert PURAYATH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES
- Publication number 20180226425
- Publication date Aug 9, 2018
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES
- Publication number 20180226426
- Publication date Aug 9, 2018
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN
- Publication number 20170040207
- Publication date Feb 9, 2017
- Applied Materials, Inc.
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Storage Element With Suspended Charge Storage Region
- Publication number 20160240546
- Publication date Aug 18, 2016
- SANDISK TECHNOLOGIES INC.
- Donovan Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL GATE SEPARATION
- Publication number 20160218018
- Publication date Jul 28, 2016
- Applied Materials, Inc.
- Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED OXIDE AND SI ETCH FOR 3D CELL CHANNEL MOBILITY IMPROVEMENTS
- Publication number 20160042968
- Publication date Feb 11, 2016
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WORDLINE 3D FLASH MEMORY AIR GAP
- Publication number 20160043099
- Publication date Feb 11, 2016
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED OXIDE RECESS AND FLOATING GATE FIN TRIMMING
- Publication number 20160035586
- Publication date Feb 4, 2016
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN
- Publication number 20160035614
- Publication date Feb 4, 2016
- Vinod R. Purayath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Resistance-Switching Memory Cell With Multiple Raised Structures In...
- Publication number 20150333105
- Publication date Nov 19, 2015
- SanDisk 3D LLC
- George Matamis
- H01 - BASIC ELECTRIC ELEMENTS

Vinod Robert Purayath

Person

Patents Grantslast 30 patents

Three-dimensional memory structure fabrication using channel replac...

Three-dimensional memory string array of thin-film ferroelectric tr...

Process for a 3-dimensional array of horizontal nor-type memory str...

Process for preparing a channel region of a thin-film transistor in...

3-dimensional memory string array of thin-film ferroelectric transi...

Methods for fabricating a 3-dimensional memory structure of nor mem...

Process for preparing a channel region of a thin-film transistor in...

Process for a 3-dimensional array of horizontal NOR-type memory str...

Methods and apparatus for three-dimensional NAND structure fabrication

3D flash memory cells which discourage cross-cell electrical tunneling

Accommodating imperfectly aligned memory holes

Charge-trap layer separation and word-line isolation in a 3-D NAND...

Accommodating imperfectly aligned memory holes

Accommodating imperfectly aligned memory holes

Charge-trap layer separation and word-line isolation for enhanced 3...

Integrated bit-line airgap formation and gate stack post clean

Non-volatile memory with flat cell structures and air gap isolation

Trench vertical NAND and method of making thereof

Non-volatile storage element with suspended charge storage region

Integrated bit-line airgap formation and gate stack post clean

Resistance-switching memory cell with multiple raised structures in...

Air gap isolation in non-volatile memory

Vertical gate separation

Method for forming resistance-switching memory cell with multiple e...

Air gaps between copper lines

Metal control gate structures and air gap isolation in non-volatile...

Integrated oxide recess and floating gate fin trimming

Non-volatile storage element with suspended charge storage region

Nanodot enhanced hybrid floating gate for non-volatile memory devices

Dopant etch selectivity control

Patents Applicationslast 30 patents

THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TR...

THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TR...

METHODS FOR FABRICATING A 3-DIMENSIONAL MEMORY STRUCTURE OF NOR MEM...

PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STR...

PROCESS FOR PREPARING A CHANNEL REGION OF A THIN-FILM TRANSISTOR IN...

3-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSI...

THREE-DIMENSIONAL MEMORY STRUCTURE FABRICATED USING REPEATED ACTIVE...

METHODS FOR FABRICATION OF 3-DIMENSIONAL NOR MEMORY ARRAYS

THREE-DIMENSIONAL MEMORY STRUCTURE FABRICATION USING CHANNEL REPLAC...

VERTICAL NOR FLASH THIN FILM TRANSISTOR STRINGS AND FABRICATION THE...

THIN-FILM STORAGE TRANSISTOR WITH FERROELECTRIC STORAGE LAYER

METHODS FOR FABRICATING A 3-DIMENSIONAL MEMORY STRUCTURE OF NOR MEM...

METHODS FOR FABRICATING A 3-DIMENSIONAL MEMORY STRUCTURE OF NOR MEM...

PROCESS FOR PREPARING A CHANNEL REGION OF A THIN-FILM TRANSISTOR IN...

PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STR...

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NAND STRUCTURE FABRICATION

MEMORY DEVICE IMPROVEMENT

ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES

3D FLASH MEMORY CELLS WHICH DISCOURAGE CROSS-CELL ELECTRICAL TUNNELING

CHARGE-TRAP LAYER SEPARATION AND WORD-LINE ISOLATION IN A 3-D NAND...

ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES

ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES

INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN

Non-Volatile Storage Element With Suspended Charge Storage Region

VERTICAL GATE SEPARATION

INTEGRATED OXIDE AND SI ETCH FOR 3D CELL CHANNEL MOBILITY IMPROVEMENTS

WORDLINE 3D FLASH MEMORY AIR GAP

INTEGRATED OXIDE RECESS AND FLOATING GATE FIN TRIMMING

INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN

Resistance-Switching Memory Cell With Multiple Raised Structures In...