Werner Graf

Person

Dresden, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Top corner rounding by implant-enhanced wet etching
- Patent number 9,023,709
- Issue date May 5, 2015
- GLOBALFOUNDRIES Inc.
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure for semiconductor devices
- Patent number 8,138,538
- Issue date Mar 20, 2012
- Qimonda AG
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with a contact structure including a portion arr...
- Patent number 8,008,729
- Issue date Aug 30, 2011
- Qimonda AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Word line to bit line spacing method and apparatus
- Patent number 7,838,928
- Issue date Nov 23, 2010
- Qimonda AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing method for an integrated semiconductor structure
- Patent number 7,361,974
- Issue date Apr 22, 2008
- Infineon Technologies AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a semiconductor structure
- Patent number 7,314,803
- Issue date Jan 1, 2008
- Infineon Technologies AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor product with a memory area a...
- Patent number 7,217,610
- Issue date May 15, 2007
- Infineon Technologies AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of treating a structured surface
- Patent number 7,208,416
- Issue date Apr 24, 2007
- Infineon Technologies AG
- Matthias Kroenke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for production of contacts on a wafer
- Patent number 7,094,674
- Issue date Aug 22, 2006
- Infineon Technologies AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a contact hole plane in a memory module
- Patent number 7,018,781
- Issue date Mar 28, 2006
- Infineon Technologies, AG
- Hans-Georg Fröhlich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor with a gate structure
- Patent number 6,927,154
- Issue date Aug 9, 2005
- Infineon Technologies AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for planarizing an isolating layer
- Patent number 6,753,236
- Issue date Jun 22, 2004
- Infineon Technologies AG
- Klaus Feldner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing transistors in integrated semiconductor circuits
- Patent number 6,586,305
- Issue date Jul 1, 2003
- Infineon Technologies AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TOP CORNER ROUNDING BY IMPLANT-ENHANCED WET ETCHING
- Publication number 20150064872
- Publication date Mar 5, 2015
- GLOBALFOUNDRIES INC.
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit with a Contact Structure Including a Portion Arr...
- Publication number 20100090285
- Publication date Apr 15, 2010
- QIMONDA AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES
- Publication number 20100090264
- Publication date Apr 15, 2010
- QIMONDA AG
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Word Line to Bit Line Spacing Method and Apparatus
- Publication number 20090302380
- Publication date Dec 10, 2009
- Qimonda AG
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming an integrated circuit having an active semicondu...
- Publication number 20080315326
- Publication date Dec 25, 2008
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Manufacturing method for an integrated semiconductor structure and...
- Publication number 20080150141
- Publication date Jun 26, 2008
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Manufacturing method for an integrated semiconductor structure
- Publication number 20070224810
- Publication date Sep 27, 2007
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for production of contacts on a wafer
- Publication number 20060276019
- Publication date Dec 7, 2006
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of treating a structured surface
- Publication number 20060172539
- Publication date Aug 3, 2006
- Infineon Technologies AG
- Matthias Kroenke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a first contact hole plane in a memory module
- Publication number 20060148227
- Publication date Jul 6, 2006
- Infineon Technologies AG
- Matthias Kronke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for producing a semiconductor structure
- Publication number 20060141756
- Publication date Jun 29, 2006
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a contact hole plane in a memory module
- Publication number 20050003308
- Publication date Jan 6, 2005
- Infineon Technologies AG
- Hans-Georg Frohlich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a semiconductor product with a memory area a...
- Publication number 20040259298
- Publication date Dec 23, 2004
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for production of contacts on a wafer
- Publication number 20040142548
- Publication date Jul 22, 2004
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate structure for a transistor and method for fabricating a transi...
- Publication number 20030215986
- Publication date Nov 20, 2003
- Werner Graf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for planarizing an isolating layer
- Publication number 20030045105
- Publication date Mar 6, 2003
- Klaus Feldner
- H01 - BASIC ELECTRIC ELEMENTS

Werner Graf

Person

Patents Grantslast 30 patents

Top corner rounding by implant-enhanced wet etching

Interconnect structure for semiconductor devices

Integrated circuit with a contact structure including a portion arr...

Word line to bit line spacing method and apparatus

Manufacturing method for an integrated semiconductor structure

Method for producing a semiconductor structure

Method for fabricating a semiconductor product with a memory area a...

Method of treating a structured surface

Method for production of contacts on a wafer

Method for fabricating a contact hole plane in a memory module

Method for fabricating a transistor with a gate structure

Method for planarizing an isolating layer

Method for producing transistors in integrated semiconductor circuits

Patents Applicationslast 30 patents

TOP CORNER ROUNDING BY IMPLANT-ENHANCED WET ETCHING

Integrated Circuit with a Contact Structure Including a Portion Arr...

INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES

Word Line to Bit Line Spacing Method and Apparatus

Method for forming an integrated circuit having an active semicondu...

Manufacturing method for an integrated semiconductor structure and...

Manufacturing method for an integrated semiconductor structure

Method for production of contacts on a wafer

Method of treating a structured surface

Method for fabricating a first contact hole plane in a memory module

Method for producing a semiconductor structure

Method for fabricating a contact hole plane in a memory module

Method for fabricating a semiconductor product with a memory area a...

Method for production of contacts on a wafer

Gate structure for a transistor and method for fabricating a transi...

Method for planarizing an isolating layer