1. Field of the Invention
The present invention relates to a manufacturing method for an integrated semiconductor structure and to a corresponding semiconductor structure.
2. Description of the Related Art
Although applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology. In particular, DRAM technology which is scaled down to below 100 nm generation provides big challenges.
Phospho-silicate glass (PSG) is used to getter mobile ions (Li, Na, K) and metal contaminants in semiconductor structures, because these elements which are still present in today's semiconductor structures deteriorate the electrical functions thereof.
In
However, as indicated with reference sign L in
According to one aspect of the invention as claimed in claim 1, a manufacturing method for an integrated semiconductor structure comprises the steps of: providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer.
According to another aspect of the present invention as claimed in claim 23, an integrated semiconductor structure comprises: a semiconductor substrate with a main surface; wiring metal layer formed above said main surface; a doped getter layer formed on said wiring metal layer; and at least one additional wiring metal layer formed on said doped getter layer.
According to another aspect of the present invention as claimed in claim 39, a semiconductor memory device comprises:
a semiconductor substrate having a main surface including a plurality of non-planar gate stacks; a planarization layer for planarizing said gate stacks; a wiring metal layer formed in or on said planarization layer; an interlevel insulating layer formed on said wiring metal layer; a doped getter layer formed on said interlevel insulating layer; and at least one additional wiring metal layer formed on said doped getter layer.
One advantage of the proposed implementation is that any underlying layer may be chosen without paying attention to gettering effects thus e.g. avoiding planarizing deficites of gettering material layers.
Preferred embodiments are listed in the respective dependent claims.
In the Figures:
a)-d) show schematic layouts for illustrating a manufacturing method for an integrated semiconductor structure according to a first embodiment of the present invention;
a)-c) show schematic layouts for illustrating a manufacturing method for an integrated semiconductor structure according to a third embodiment of the present invention;
In the Figures, identical reference signs denote equivalent or functionally equivalent components.
a)-d) show schematic layouts for illustrating a manufacturing method for an integrated semiconductor structure according to a first embodiment of the present invention.
In
In this first embodiment, a spin-on glass layer SOL is used as a planarization and gap fill layer which exhibits excellent property regarding gap fill and essentially exhibits no unwanted voids. However, this spin-on glass layer SOL does not contain any getter material such as phosphorous.
On top of the spin-on glass layer SOL, a lowest level wiring metal layer MO is deposited and structured, e.g. a tungsten layer, by masking and etching process steps.
In a next process step which is shown in
In a subsequent process step which is shown in
Then, as shown in
In the semiconductor structure shown in
Although described here as pure phospho-silicate glass layer, it is of course possible to have a mixed layer such as a boro-phospho-silicate glass layer, typically with a phosphorous content between 0.01%-10% by weight. Even though the mentioned phosphorous content may be advantageous it is only an example and other contents may be possible.
According to the second embodiment shown in
a)-c) show schematic layouts for illustrating a manufacturing method for an integrated semiconductor structure according to a third embodiment of the present invention.
The process state shown in
Namely, in this third embodiment, the interlevel insulating layer ILD0 is a high-density plasma-oxide layer which after deposition shows a non-planar surface. After deposition of this interlevel insulating layer ILD0, a getter layer GL′ made of phospho-silicate glass is deposited over the non-planar surface of the interlevel insulating layer ILD0 and thereafter polished back in chemical-mechanical polishing step, so as to reach the process state shown in
The contact K formation step shown in
Also, the second level wiring metal layer M1 formation step shown in
According to the fourth embodiment, the getter layer GL′ is deposited without any doping on the interlevel insulating layer ILD0, e.g. as pure silicate-glass. Thereafter and before formation of the contacts K an ion-implantation step for implanting phosphorous ions into the getter layer GL′ is performed. The parameters of this ion-implantation step are chosen such that a roughening of a surface area of the getter layer GL′ is effected which improves the adhesion to the second level wiring metal layer M1 and allows omission of the adhesion layer described in connection with the second embodiment shown in
However, it is possible as well to additionally add said adhesion layer to the embodiment shown in
Although the present invention has been described with reference to a preferred embodiment, it is not limited thereto, but can be modified in various manners which are obvious for a person skilled in the art. Thus, it is intended that the present invention is only limited by the scope of the claims attached herewith.
Although not shown here, the lowest level metal wiring layer M0 and corresponding interlevel insulating layer ILD0 can be formed in damascene-level type, i.e. metal and interlevel dielectric extend to the same upper height.
Such a damascene technique would be performed by forming a insulating layer on said main surface, etching trenches in said insulating layer, depositing said wiring metal layer above said trenched insulating layer, and planarizing said wiring metal layer such that it only remains in said trenches.
Moreover, said metal layers can be any level metal layers.
Moreover, if necessary, the getter layer can be annealed immediately after its formation, especially if the getter layer is implanted with phosphorous ions after its deposition.
Moreover, said interlevel insulating layer ILD0 could comprise a HDP oxide layer and a TEOS layer deposited thereon. If the underlying structure is non-planar said TEOS layer could be planarized in a planarizing step before the getter layer is deposited thereon.
Number | Date | Country | Kind |
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102006060770.8 | Dec 2006 | DE | national |