WILFRED GOMES

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hyperchip
- Patent number 12,355,002
- Issue date Jul 8, 2025
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded memory IC's with power supply droop circuitry coupled to f...
- Patent number 12,327,581
- Issue date Jun 10, 2025
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Grant
Vertically stacked and bonded memory arrays
- Patent number 12,327,809
- Issue date Jun 10, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked backend memory with resistive switching devices
- Patent number 12,310,032
- Issue date May 20, 2025
- Intel Corporation
- Wilfred Gomes
Information Patent Grant
Decoupling capacitors and methods of fabrication
- Patent number 12,310,001
- Issue date May 20, 2025
- Intel Corporation
- Juan G. Alzate-Vinasco
Information Patent Grant
Hybrid manufacturing for integrated circuit devices and assemblies
- Patent number 12,278,229
- Issue date Apr 15, 2025
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated three-dimensional (3D) DRAM cache
- Patent number 12,271,306
- Issue date Apr 8, 2025
- Intel Corporation
- Wilfred Gomes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layered optical integrated circuit assembly with a monocrysta...
- Patent number 12,197,007
- Issue date Jan 14, 2025
- Intel Corporation
- Abhishek A. Sharma
- G02 - OPTICS
Information Patent Grant
Three-dimensional capacitors with double metal electrodes
- Patent number 12,176,147
- Issue date Dec 24, 2024
- Intel Corporation
- James D. Waldemer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit assemblies with direct chip attach to circuit bo...
- Patent number 12,170,273
- Issue date Dec 17, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid manufacturing for integrating photonic and electronic compon...
- Patent number 12,147,083
- Issue date Nov 19, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gallium nitride (GAN) three-dimensional integrated circuit technology
- Patent number 12,148,747
- Issue date Nov 19, 2024
- Intel Corporation
- Han Wui Then
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrays of double-sided dram cells including capacitors on the front...
- Patent number 12,120,865
- Issue date Oct 15, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory arrays with layer selector transistors
- Patent number 12,114,479
- Issue date Oct 8, 2024
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Grant
Hyperchip
- Patent number 12,074,138
- Issue date Aug 27, 2024
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional nanoribbon-based dynamic random-access memory
- Patent number 12,058,849
- Issue date Aug 6, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hyperchip
- Patent number 11,984,430
- Issue date May 14, 2024
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package on active silicon semiconductor packages
- Patent number 11,978,727
- Issue date May 7, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic package with three-dimensional (3D) monolithic memo...
- Patent number 11,901,347
- Issue date Feb 13, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distributed semiconductor die and package architecture
- Patent number 11,894,359
- Issue date Feb 6, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, system and method for providing inductor structures
- Patent number 11,830,829
- Issue date Nov 28, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hyperchip
- Patent number 11,824,041
- Issue date Nov 21, 2023
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid manufacturing for integrated circuit devices and assemblies
- Patent number 11,817,442
- Issue date Nov 14, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid manufacturing of microeletronic assemblies with first and se...
- Patent number 11,756,886
- Issue date Sep 12, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, method and system for providing a stacked arrangement of in...
- Patent number 11,749,663
- Issue date Sep 5, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin film transistor based memory cells on both sides of a layer of...
- Patent number 11,690,211
- Issue date Jun 27, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die interconnection scheme for providing a high yielding process fo...
- Patent number 11,652,060
- Issue date May 16, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge hub tiling architecture
- Patent number 11,569,173
- Issue date Jan 31, 2023
- Intel Corporation
- Andrew P. Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, system and method for providing inductor structures
- Patent number 11,387,198
- Issue date Jul 12, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, method and system for providing a stacked arrangement of in...
- Patent number 11,373,987
- Issue date Jun 28, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE DO...
- Publication number 20250210587
- Publication date Jun 26, 2025
- Intel Corporation
- Nicolas Butzen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH HIGH CAPA...
- Publication number 20250201768
- Publication date Jun 19, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES FOR HIGH CAPAC...
- Publication number 20250201793
- Publication date Jun 19, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE CO...
- Publication number 20250201766
- Publication date Jun 19, 2025
- Intel Corporation
- Nicolas Butzen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH BOUNDARY...
- Publication number 20250201767
- Publication date Jun 19, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID MANUFACTURING FOR INTEGRATED CIRCUIT DEVICES AND ASSEMBLIES
- Publication number 20250201797
- Publication date Jun 19, 2025
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS
- Publication number 20250159953
- Publication date May 15, 2025
- Intel Corporation
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIEN...
- Publication number 20250140741
- Publication date May 1, 2025
- Intel Corporation
- Rajiv Mongia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYERED OPTICAL INTEGRATED CIRCUIT ASSEMBLY WITH A MONOCRYSTA...
- Publication number 20250116812
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek A. Sharma
- G02 - OPTICS
Information Patent Application
STACKED MEMORY LAYERS WITH UNIFORM ACCESS
- Publication number 20250107107
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
- Publication number 20250107108
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
- Publication number 20250104760
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO...
- Publication number 20250095693
- Publication date Mar 20, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY LAYERS AT OPPOSING SIDES OF A COMPLEMENTARY METAL-OXIDE SEMI...
- Publication number 20250098179
- Publication date Mar 20, 2025
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE RE...
- Publication number 20250079398
- Publication date Mar 6, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH A COOLING...
- Publication number 20250079263
- Publication date Mar 6, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AS A SOLID STA...
- Publication number 20250079399
- Publication date Mar 6, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER IN...
- Publication number 20250062278
- Publication date Feb 20, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY
- Publication number 20250040231
- Publication date Jan 30, 2025
- Intel Corporation
- Han Wui THEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARRAYS OF DOUBLE-SIDED DRAM CELLS INCLUDING CAPACITORS ON THE FRONT...
- Publication number 20250031362
- Publication date Jan 23, 2025
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID MANUFACTURING FOR INTEGRATING PHOTONIC AND ELECTRONIC COMPON...
- Publication number 20250020873
- Publication date Jan 16, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL FLOATING BODY MEMORY
- Publication number 20250008723
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL WITH TRANSISTOR HAVING INCREASED LEAKAGE CURRENT
- Publication number 20240431092
- Publication date Dec 26, 2024
- Intel Corporation
- Abhishek A. Sharma
Information Patent Application
MEMORY WITH ONE ACCESS TRANSISTOR COUPLED TO MULTIPLE CAPACITORS
- Publication number 20240431117
- Publication date Dec 26, 2024
- Intel Corporation
- Abhishek A. Sharma
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH CONDUCTIVE LINES EXTENDING OVER SCR...
- Publication number 20240429162
- Publication date Dec 26, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS
- Publication number 20240389300
- Publication date Nov 21, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYPERCHIP
- Publication number 20240243099
- Publication date Jul 18, 2024
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING ROUTING ACROSS LAYERS OF CHANN...
- Publication number 20240222271
- Publication date Jul 4, 2024
- Intel Corporation
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222321
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...
- Publication number 20240222326
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS

WILFRED GOMES

Person

Patents Grantslast 30 patents

Hyperchip

Embedded memory IC's with power supply droop circuitry coupled to f...

Vertically stacked and bonded memory arrays

Stacked backend memory with resistive switching devices

Decoupling capacitors and methods of fabrication

Hybrid manufacturing for integrated circuit devices and assemblies

Integrated three-dimensional (3D) DRAM cache

Multi-layered optical integrated circuit assembly with a monocrysta...

Three-dimensional capacitors with double metal electrodes

Integrated circuit assemblies with direct chip attach to circuit bo...

Hybrid manufacturing for integrating photonic and electronic compon...

Gallium nitride (GAN) three-dimensional integrated circuit technology

Arrays of double-sided dram cells including capacitors on the front...

Three-dimensional memory arrays with layer selector transistors

Hyperchip

Three-dimensional nanoribbon-based dynamic random-access memory

Hyperchip

Package on active silicon semiconductor packages

Microelectronic package with three-dimensional (3D) monolithic memo...

Distributed semiconductor die and package architecture

Device, system and method for providing inductor structures

Hyperchip

Hybrid manufacturing for integrated circuit devices and assemblies

Hybrid manufacturing of microeletronic assemblies with first and se...

Device, method and system for providing a stacked arrangement of in...

Thin film transistor based memory cells on both sides of a layer of...

Die interconnection scheme for providing a high yielding process fo...

Bridge hub tiling architecture

Device, system and method for providing inductor structures

Device, method and system for providing a stacked arrangement of in...

Patents Applicationslast 30 patents

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE DO...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH HIGH CAPA...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES FOR HIGH CAPAC...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE CO...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH BOUNDARY...

HYBRID MANUFACTURING FOR INTEGRATED CIRCUIT DEVICES AND ASSEMBLIES

INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS

PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIEN...

MULTI-LAYERED OPTICAL INTEGRATED CIRCUIT ASSEMBLY WITH A MONOCRYSTA...

STACKED MEMORY LAYERS WITH UNIFORM ACCESS

MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION

STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE

CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO...

MEMORY LAYERS AT OPPOSING SIDES OF A COMPLEMENTARY METAL-OXIDE SEMI...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE RE...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH A COOLING...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AS A SOLID STA...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER IN...

GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY

ARRAYS OF DOUBLE-SIDED DRAM CELLS INCLUDING CAPACITORS ON THE FRONT...

HYBRID MANUFACTURING FOR INTEGRATING PHOTONIC AND ELECTRONIC COMPON...

THREE-DIMENSIONAL FLOATING BODY MEMORY

MEMORY CELL WITH TRANSISTOR HAVING INCREASED LEAKAGE CURRENT

MEMORY WITH ONE ACCESS TRANSISTOR COUPLED TO MULTIPLE CAPACITORS

INTEGRATED CIRCUIT DEVICES WITH CONDUCTIVE LINES EXTENDING OVER SCR...

THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS

HYPERCHIP

INTEGRATED CIRCUIT STRUCTURES HAVING ROUTING ACROSS LAYERS OF CHANN...

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...

PACKAGE ARCHITECTURE WITH MEMORY CHIPS HAVING DIFFERENT PROCESS REG...