William Hsu

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 12,224,350
- Issue date Feb 11, 2025
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate-less electrostatic discharge (ESD) integrated circuit str...
- Patent number 12,166,031
- Issue date Dec 10, 2024
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 12,068,314
- Issue date Aug 20, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated nanowire and nanoribbon patterning in transistor manufac...
- Patent number 12,014,959
- Issue date Jun 18, 2024
- Intel Corporation
- Leonard P Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 11,990,472
- Issue date May 21, 2024
- Intel Corporation
- Leonard P. Guler
- G11 - INFORMATION STORAGE
Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,929,396
- Issue date Mar 12, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Gate-all-around integrated circuit structures having devices with s...
- Patent number 11,908,856
- Issue date Feb 20, 2024
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,901,458
- Issue date Feb 13, 2024
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures fabricated using alte...
- Patent number 11,894,368
- Issue date Feb 6, 2024
- Intel Corporation
- Sudipto Naskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar integrated circuit structures having mitigated source or...
- Patent number 11,869,891
- Issue date Jan 9, 2024
- Intel Corporation
- Jun Sung Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanowire transistor structure and method of shaping
- Patent number 11,869,973
- Issue date Jan 9, 2024
- Intel Corporation
- Erica J. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 11,855,223
- Issue date Dec 26, 2023
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having adjacent deep...
- Patent number 11,837,641
- Issue date Dec 5, 2023
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having devices with c...
- Patent number 11,824,116
- Issue date Nov 21, 2023
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having adjacent struc...
- Patent number 11,799,009
- Issue date Oct 24, 2023
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FIN shaping using templates and integrated circuit structures resul...
- Patent number 11,749,733
- Issue date Sep 5, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation schemes for gate-all-around transistor devices
- Patent number 11,705,518
- Issue date Jul 18, 2023
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having fin stack isol...
- Patent number 11,594,637
- Issue date Feb 28, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-Fin isolation schemes for gate-all-around transistor devices
- Patent number 11,588,052
- Issue date Feb 21, 2023
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DEPOP using cyclic selective spacer etch
- Patent number 11,569,370
- Issue date Jan 31, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Increased transistor source/drain contact area using sacrificial so...
- Patent number 11,495,672
- Issue date Nov 8, 2022
- Intel Corporation
- Dax M. Crum
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate edge architecture with alternate channel material
- Patent number 11,456,357
- Issue date Sep 27, 2022
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,404,578
- Issue date Aug 2, 2022
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,342,411
- Issue date May 24, 2022
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Isolation schemes for gate-all-around transistor devices
- Patent number 11,335,807
- Issue date May 17, 2022
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin shaping using templates and integrated circuit structures resul...
- Patent number 11,302,790
- Issue date Apr 12, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 11,233,152
- Issue date Jan 25, 2022
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated nanowire and nanoribbon patterning in transistor manufac...
- Patent number 11,164,790
- Issue date Nov 2, 2021
- Intel Corporation
- Leonard P Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor layer between source/drain regions and gate spacers
- Patent number 11,152,461
- Issue date Oct 19, 2021
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20240363628
- Publication date Oct 31, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Cavity Spacer for Nanowire Transistors
- Publication number 20240347595
- Publication date Oct 17, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...
- Publication number 20240243203
- Publication date Jul 18, 2024
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20240178226
- Publication date May 30, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEVICES WITH S...
- Publication number 20240145471
- Publication date May 2, 2024
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...
- Publication number 20240145598
- Publication date May 2, 2024
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES FABRICATED USING ALTE...
- Publication number 20240120335
- Publication date Apr 11, 2024
- Intel Corporation
- Sudipto NASKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...
- Publication number 20240096896
- Publication date Mar 21, 2024
- Intel Corporation
- Jun Sung KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING
- Publication number 20240088296
- Publication date Mar 14, 2024
- Intel Corporation
- Erica J. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE AND DRAIN REGIONS FOR LATERALLY ADJACENT GATE-ALL-AROUND (GA...
- Publication number 20240071831
- Publication date Feb 29, 2024
- Intel Corporation
- Chang Wan Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT DEEP...
- Publication number 20240055497
- Publication date Feb 15, 2024
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEVICES WITH C...
- Publication number 20240038889
- Publication date Feb 1, 2024
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...
- Publication number 20240030348
- Publication date Jan 25, 2024
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT STRUC...
- Publication number 20240006504
- Publication date Jan 4, 2024
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTR...
- Publication number 20230420574
- Publication date Dec 28, 2023
- Intel Corporation
- Seung Hoon Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SC...
- Publication number 20230197818
- Publication date Jun 22, 2023
- Intel Corporation
- Nitesh Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...
- Publication number 20230163215
- Publication date May 25, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DOPED SUBFIN
- Publication number 20230088753
- Publication date Mar 23, 2023
- Intel Corporation
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANORIBBON SUB-FIN ISOLATION BY BACKSIDE SI SUBSTRATE REMOVAL ETCH...
- Publication number 20220416027
- Publication date Dec 29, 2022
- Intel Corporation
- William HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUMMY GATE PATTERNING LINES AND INTEGRATED CIRCUIT STRUCTURES RESUL...
- Publication number 20220415780
- Publication date Dec 29, 2022
- Intel Corporation
- William HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GATE HEIGHT RE...
- Publication number 20220416042
- Publication date Dec 29, 2022
- Intel Corporation
- William HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANORIBBON SUBFIN ISOLATION BY BACKSIDE SILICON SUBSTRATE REMOVAL W...
- Publication number 20220416041
- Publication date Dec 29, 2022
- Intel Corporation
- Mohammad HASAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE ALIGNED FIN CUT FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABR...
- Publication number 20220392808
- Publication date Dec 8, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...
- Publication number 20220336668
- Publication date Oct 20, 2022
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAVITY SPACER FOR NANOWIRE TRANSISTORS
- Publication number 20220246721
- Publication date Aug 4, 2022
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES
- Publication number 20220246759
- Publication date Aug 4, 2022
- Intel Corporation
- RISHABH MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...
- Publication number 20220199792
- Publication date Jun 23, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE-LESS ELECTROSTATIC DISCHARGE (ESD) INTEGRATED CIRCUIT STR...
- Publication number 20220199610
- Publication date Jun 23, 2022
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...
- Publication number 20220102557
- Publication date Mar 31, 2022
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20220093592
- Publication date Mar 24, 2022
- Intel Corporation
- Leonard P. GULER
- G11 - INFORMATION STORAGE

William Hsu

Person

Patents Grantslast 30 patents

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Substrate-less electrostatic discharge (ESD) integrated circuit str...

Fabrication of gate-all-around integrated circuit structures having...

Integrated nanowire and nanoribbon patterning in transistor manufac...

Fabrication of gate-all-around integrated circuit structures having...

Cavity spacer for nanowire transistors

Gate-all-around integrated circuit structures having devices with s...

Dielectric isolation layer between a nanowire transistor and a subs...

Gate-all-around integrated circuit structures fabricated using alte...

Non-planar integrated circuit structures having mitigated source or...

Nanowire transistor structure and method of shaping

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Gate-all-around integrated circuit structures having adjacent deep...

Gate-all-around integrated circuit structures having devices with c...

Gate-all-around integrated circuit structures having adjacent struc...

FIN shaping using templates and integrated circuit structures resul...

Isolation schemes for gate-all-around transistor devices

Gate-all-around integrated circuit structures having fin stack isol...

Sub-Fin isolation schemes for gate-all-around transistor devices

DEPOP using cyclic selective spacer etch

Increased transistor source/drain contact area using sacrificial so...

Self-aligned gate edge architecture with alternate channel material

Dielectric isolation layer between a nanowire transistor and a subs...

Cavity spacer for nanowire transistors

Isolation schemes for gate-all-around transistor devices

Fin shaping using templates and integrated circuit structures resul...

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Integrated nanowire and nanoribbon patterning in transistor manufac...

Semiconductor layer between source/drain regions and gate spacers

Patents Applicationslast 30 patents

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

Cavity Spacer for Nanowire Transistors

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEVICES WITH S...

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES FABRICATED USING ALTE...

NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...

NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING

SOURCE AND DRAIN REGIONS FOR LATERALLY ADJACENT GATE-ALL-AROUND (GA...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT DEEP...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEVICES WITH C...

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADJACENT STRUC...

MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTR...

FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SC...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DOPED SUBFIN

NANORIBBON SUB-FIN ISOLATION BY BACKSIDE SI SUBSTRATE REMOVAL ETCH...

DUMMY GATE PATTERNING LINES AND INTEGRATED CIRCUIT STRUCTURES RESUL...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GATE HEIGHT RE...

NANORIBBON SUBFIN ISOLATION BY BACKSIDE SILICON SUBSTRATE REMOVAL W...

GATE ALIGNED FIN CUT FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABR...

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...

CAVITY SPACER FOR NANOWIRE TRANSISTORS

ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES

FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...

SUBSTRATE-LESS ELECTROSTATIC DISCHARGE (ESD) INTEGRATED CIRCUIT STR...

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...