Xiaoying GUO

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
First layer interconnect first on carrier approach for EMIB patch
- Patent number 12,354,992
- Issue date Jul 8, 2025
- Intel Corporation
- Changhua Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus to reduce defects in interconnects between se...
- Patent number 12,341,117
- Issue date Jun 24, 2025
- Intel Corporation
- Kyle McElhinny
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus to reduce defects in interconnects between se...
- Patent number 12,334,422
- Issue date Jun 17, 2025
- Intel Corporation
- Kyle McElhinny
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chiplet first architecture for die tiling applications
- Patent number 12,308,329
- Issue date May 20, 2025
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Airgap structures for high speed signal integrity
- Patent number 12,255,130
- Issue date Mar 18, 2025
- Intel Corporation
- Hongxia Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Coreless architecture and processing strategy for EMIB-based substr...
- Patent number 12,142,567
- Issue date Nov 12, 2024
- Intel Corporation
- Xiao Di Sun Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chiplet first architecture for die tiling applications
- Patent number 11,990,427
- Issue date May 21, 2024
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chiplet first architecture for die tiling applications
- Patent number 11,973,041
- Issue date Apr 30, 2024
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Architecture to manage FLI bump height delta and reliability needs...
- Patent number 11,955,448
- Issue date Apr 9, 2024
- Intel Corporation
- Jung Kyu Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch barrier for microelectronic packaging conductive structures
- Patent number 11,948,898
- Issue date Apr 2, 2024
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies having conductive structures with differ...
- Patent number 11,942,334
- Issue date Mar 26, 2024
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chiplet first architecture for die tiling applications
- Patent number 11,769,735
- Issue date Sep 26, 2023
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-situ component fabrication of a highly efficient, high inductanc...
- Patent number 11,404,389
- Issue date Aug 2, 2022
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
First layer interconnect first on carrier approach for EMIB patch
- Patent number 11,088,103
- Issue date Aug 10, 2021
- Intel Corporation
- Changhua Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOW TEMPERATURE SOLDER INTERCONNECT FOR PACKAGE PITCH SCALING
- Publication number 20250218998
- Publication date Jul 3, 2025
- Intel Corporation
- Bohan SHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH PILLAR-FIRST CONDUCTIVE VIA FORMATI...
- Publication number 20250218880
- Publication date Jul 3, 2025
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO EMBED A SEMICONDUCTOR DEVICE IN A GLASS CORE
- Publication number 20250218957
- Publication date Jul 3, 2025
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLOW ENHANCED DUMMY STRUCTURE TO ENABLE CAPILLARY FLOW BASED SIDEWA...
- Publication number 20250220818
- Publication date Jul 3, 2025
- Intel Corporation
- Bohan SHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEEP TRENCH CAPACITORS IN MULTI-CORE INTEGRATED CIRCUIT DEVICE PACK...
- Publication number 20250219028
- Publication date Jul 3, 2025
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES INCLUDING CAVITY-LESS ENCAPSULATED DIES
- Publication number 20250218926
- Publication date Jul 3, 2025
- Intel Corporation
- Minglu Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH STRENGTHENED GLASS CORES
- Publication number 20250210426
- Publication date Jun 26, 2025
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH PRE-SINGULATION EDGE FEATURES IN GL...
- Publication number 20250192069
- Publication date Jun 12, 2025
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH POST-SINGULATION EDGE FEATURES IN G...
- Publication number 20250192070
- Publication date Jun 12, 2025
- Intel Corporation
- Jesse C. Jones
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED BRIDGE WITH THROUGH SILICON VIA BONDING ARCHITECTURES
- Publication number 20250192059
- Publication date Jun 12, 2025
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIRECT BONDING FOR EMBEDDED BRIDGES WITH VIAS
- Publication number 20250183180
- Publication date Jun 5, 2025
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH THROUGH-GLASS VIA STRESS ALLEVIATIO...
- Publication number 20250183182
- Publication date Jun 5, 2025
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS CORE PROTECTION USING PERIPHERAL BUFFER LAYERS
- Publication number 20250112136
- Publication date Apr 3, 2025
- Intel Corporation
- Bohan SHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS FOR CAPILLARY UNDERFILL OF EMBEDDED DEVICES
- Publication number 20250112085
- Publication date Apr 3, 2025
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTROLLING SUBSTRATE BUMP HEIGHT
- Publication number 20250112164
- Publication date Apr 3, 2025
- Intel Corporation
- Bohan SHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STIFFENER ARCHITECTURES FOR GLASS EDGE PROTECTION
- Publication number 20250106983
- Publication date Mar 27, 2025
- Intel Corporation
- Bohan SHAN
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MICROELECTRONIC ASSEMBLIES INCLUDING A PHOTOIMAGEABLE DIELECTRIC FO...
- Publication number 20250006645
- Publication date Jan 2, 2025
- Intel Corporation
- Xiao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
2D FILLERS FOR REDUCED CTE FOR PID
- Publication number 20240332125
- Publication date Oct 3, 2024
- Intel Corporation
- Kyle ARRINGTON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO IMPROVE...
- Publication number 20240312865
- Publication date Sep 19, 2024
- Intel Corporation
- Kyle Arrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
- Publication number 20240250043
- Publication date Jul 25, 2024
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SEMICONDUCTOR PACKAGE AND METHOD
- Publication number 20240219655
- Publication date Jul 4, 2024
- Intel Corporation
- Haobo Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SEMICONDUCTOR PACKAGE AND METHOD
- Publication number 20240219660
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- G02 - OPTICS
Information Patent Application
DIE ATTACH IN GLASS CORE PACKAGE THROUGH ORGANIC-TO-ORGANIC BONDING
- Publication number 20240222345
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR ATTACHING AN OPTICAL COMPONENT USING HYBRI...
- Publication number 20240222243
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO PRODUCE...
- Publication number 20240222259
- Publication date Jul 4, 2024
- Intel Corporation
- Haobo Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR OPTICAL THERMAL TREATMENT IN SEMICONDUCTO...
- Publication number 20240222301
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO REDUCE SOLDER BUMP BRIDGING BETWEEN TWO SU...
- Publication number 20240222304
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL LAYER WITH ROUGHENED SURFACES
- Publication number 20240222136
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS SUBSTRATE DEVICE WITH PLATED THROUGH HOLES
- Publication number 20240222257
- Publication date Jul 4, 2024
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO PREVENT OVER-ETCH IN SEMICONDUCTOR PACKAGES
- Publication number 20240222283
- Publication date Jul 4, 2024
- Intel Corporation
- Hongxia Feng
- H01 - BASIC ELECTRIC ELEMENTS

Xiaoying GUO

Person

Patents Grantslast 30 patents

First layer interconnect first on carrier approach for EMIB patch

Methods and apparatus to reduce defects in interconnects between se...

Methods and apparatus to reduce defects in interconnects between se...

Chiplet first architecture for die tiling applications

Airgap structures for high speed signal integrity

Coreless architecture and processing strategy for EMIB-based substr...

Chiplet first architecture for die tiling applications

Chiplet first architecture for die tiling applications

Architecture to manage FLI bump height delta and reliability needs...

Etch barrier for microelectronic packaging conductive structures

Microelectronic assemblies having conductive structures with differ...

Chiplet first architecture for die tiling applications

In-situ component fabrication of a highly efficient, high inductanc...

First layer interconnect first on carrier approach for EMIB patch

Patents Applicationslast 30 patents

LOW TEMPERATURE SOLDER INTERCONNECT FOR PACKAGE PITCH SCALING

MICROELECTRONIC ASSEMBLIES WITH PILLAR-FIRST CONDUCTIVE VIA FORMATI...

METHODS AND APPARATUS TO EMBED A SEMICONDUCTOR DEVICE IN A GLASS CORE

FLOW ENHANCED DUMMY STRUCTURE TO ENABLE CAPILLARY FLOW BASED SIDEWA...

DEEP TRENCH CAPACITORS IN MULTI-CORE INTEGRATED CIRCUIT DEVICE PACK...

MICROELECTRONIC ASSEMBLIES INCLUDING CAVITY-LESS ENCAPSULATED DIES

MICROELECTRONIC ASSEMBLIES WITH STRENGTHENED GLASS CORES

MICROELECTRONIC ASSEMBLIES WITH PRE-SINGULATION EDGE FEATURES IN GL...

MICROELECTRONIC ASSEMBLIES WITH POST-SINGULATION EDGE FEATURES IN G...

EMBEDDED BRIDGE WITH THROUGH SILICON VIA BONDING ARCHITECTURES

DIRECT BONDING FOR EMBEDDED BRIDGES WITH VIAS

MICROELECTRONIC ASSEMBLIES WITH THROUGH-GLASS VIA STRESS ALLEVIATIO...

GLASS CORE PROTECTION USING PERIPHERAL BUFFER LAYERS

APPARATUS AND METHODS FOR CAPILLARY UNDERFILL OF EMBEDDED DEVICES

CONTROLLING SUBSTRATE BUMP HEIGHT

STIFFENER ARCHITECTURES FOR GLASS EDGE PROTECTION

MICROELECTRONIC ASSEMBLIES INCLUDING A PHOTOIMAGEABLE DIELECTRIC FO...

2D FILLERS FOR REDUCED CTE FOR PID

METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO IMPROVE...

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

OPTICAL SEMICONDUCTOR PACKAGE AND METHOD

OPTICAL SEMICONDUCTOR PACKAGE AND METHOD

DIE ATTACH IN GLASS CORE PACKAGE THROUGH ORGANIC-TO-ORGANIC BONDING

APPARATUS AND METHOD FOR ATTACHING AN OPTICAL COMPONENT USING HYBRI...

METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO PRODUCE...

METHODS AND APPARATUS FOR OPTICAL THERMAL TREATMENT IN SEMICONDUCTO...

METHODS AND APPARATUS TO REDUCE SOLDER BUMP BRIDGING BETWEEN TWO SU...

ELECTRICAL LAYER WITH ROUGHENED SURFACES

GLASS SUBSTRATE DEVICE WITH PLATED THROUGH HOLES

METHODS AND APPARATUS TO PREVENT OVER-ETCH IN SEMICONDUCTOR PACKAGES