Patent Application
20250218957
This disclosure relates generally to semiconductor packages and, more particularly, to methods and apparatus to embed a semiconductor device in a glass core.
In many electronic devices, integrated circuit (IC) chips and/or semiconductor dies are connected to larger circuit boards such as motherboards and/or other types of printed circuit boards (PCBs) via a package substrate. Some known IC packages utilize voltage regulators for power delivery applications. In some instances, capacitors and/or other semiconductor devices used for such voltage regulators can be included in the package substrate for an IC package.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
As shown in the illustrated example, each of the dies 106, 108 is electrically and mechanically coupled to the substrate 110 via corresponding arrays of interconnects 114. In
As shown in
As used herein, the bridge bumps 118 are bumps on the dies 106, 108 through which electrical signals pass between different ones of the dies 106, 108 within the package 100. Thus, as shown in the illustrated example, the bridge bumps 118 of the first die 106 are electrically coupled to the bridge bumps 118 of the second die 108 via an interconnect bridge 126 embedded in the package substrate 110. As represented in
For purposes of illustration, the internal interconnects 124 are shown as straight lines extending directly between the pads 104 on the bottom surface 105 and the contact pads on the inner surface 122. However, in some examples, the internal interconnects 124 are defined by traces or routing in separate conductive (e.g., metal) layers within build-up regions 128 on one or both sides of a substrate core 130 in the package substrate 110. In such examples, the build-up regions 128 include dielectric layers to separate the different conductive layers. In such examples, the traces or routing in the different conductive layers are electrically coupled (to define the complete electrical path of the internal interconnects 124) by conductive (e.g., metal) vias extending between the different conductive layers. Further, in some examples, the internal interconnects 124 include vias that extend through the substrate core 130.
In some examples, the substrate core 130 is a glass substrate or core. In some examples, glass substrates (e.g., the glass core 130) includes quartz, fused silica, and/or borosilicate glass. In some examples, glass substrates (e.g., the glass core 130) includes at least 20% (by weight) of each of silicon (Si) and oxygen (O). In other examples, glass substrates (e.g., the glass core 130) includes greater amounts of at least one of silicon or oxygen (e.g., at least 25 wt %, at least 30 wt %, at least 35 wt %, at least 40 wt %, etc.). In some examples, glass substrates (e.g., the glass core 130) includes at least 5% (by weight) of aluminum (Al). In accordance with the present disclosure, glass substrates (e.g., the glass core 130) include at least one glass layer and do not include epoxy and does not include glass fibers (e.g., does not include an epoxy-based prepreg layer with glass cloth). In some examples, glass substrates (e.g., the glass core 130) correspond to a single piece of glass that extends the full height/thickness of the core. In some examples, the glass core 130 has a rectangular shape that is substantially coextensive, in plan view, with the layers above and below the core (e.g., substantially coextensive with the build-up regions 128). The substrate core 130, whether an organic core or a glass core, provides stiffness and mechanical support or strength for the package substrate 110 and the rest of the package 100. Thus, the substrate core 130 is an example means for strengthening the package substrate 110. In some examples, the thickness of the core 130 is driven by the size (e.g., footprint) of the package 100. For example, in some instances, larger packages 100 include a substrate 110 with a larger (e.g., thicker) core 130 as compared with smaller packages 100 where the core does not need to be as thick.
As shown in the illustrated example, the substrate core 130 includes an example cavity 132 in which an example semiconductor device 134 is embedded. In some examples, the semiconductor device 134 is a passive semiconductor die (e.g., a die that does not include transistors). In this example, the semiconductor device 134 is a deep trench capacitor die (also referred to herein as a deep trench capacitor for short). In some such examples, the deep trench capacitor is used to enable efficient power delivery to a fully integrated voltage regulator within the first die 106 in the IC package 100. In other examples, other types of semiconductor devices can be embedded within the cavity 132 of the substrate core 130 in addition to or instead of a deep trench capacitor. In some examples, more than one semiconductor device 134 can be embedded within the cavity 132 of the substrate core 130. In some examples, the substrate core 130 can include multiple cavities each containing one or more separate semiconductor devices 134.
As noted above, in this example, the semiconductor device 134 is a deep trench capacitor and may be referred to as such herein. As shown in the illustrated example, the deep trench capacitor 134 is electrically coupled to the first die 106. In some examples, the deep trench capacitor 134 is positioned in close proximity to the first die 106 (e.g., within the substrate core 130 rather than spaced farther away like land-side capacitors) to reduce inductance and parasitic effects, thereby increasing the effectiveness of the capacitor 134 (and/or achieving a given capacitance with a smaller sized capacitor). However, a challenge with embedding a deep trench capacitor 134 within a core 130 of a substrate arises from the thickness mismatch between the deep trench capacitor 134 and the core 130. In this example, the deep trench capacitor 134 is constructed through wafer-level processing from a semiconductor (e.g., silicon) wafer. Due to the nature of such wafer-level processing, the deep trench capacitor 134 has a thickness 136 limited to less than or equal to approximately 800 micrometers (μm) or less (e.g., less than or equal to approximately 700 μm, less than or equal to approximately 650 μm, less than or equal to approximately 600 μm, etc.). By contrast, the substrate core 130 can be significantly thicker, especially for larger packages as noted above. For instance, in some examples, the core 130 has a thickness 138 that is at least 20% greater than the thickness 136 of the deep trench capacitor 134 or more (e.g., at least 25% greater, at least 30% greater, at least 50% greater, at least 75% greater, at least twice as great, etc.). More specifically, in some examples, the thickness 138 of the core 130 is greater than approximately 800 μm or more (e.g., greater than or equal to approximately 1 millimeter (mm) (e.g., 1000 μm), greater than or equal to approximately 1.2 mm, greater than or equal to approximately 1.4 mm, greater than or equal to approximately 1.5 mm, etc.). Thus, as shown in
The mismatch between the thicknesses 136, 138 of the deep trench capacitor 134 and the core 130 presents challenges in positioning the deep trench capacitor 134 within the cavity 132 of the core 130. Specifically, the relatively small size of the deep trench capacitor 134 can result in misalignments in any of the x, y, and z axes and/or rotational shifting or tilting because of the difficulty in securing the deep trench capacitor in place. In particular, the use of adhesives and/or an encapsulant (e.g., an example adhesive material 142 such as a dispensable liquid adhesive) to hold the deep trench capacitor 134 in place can be difficult because of the large space within the cavity 132 that needs to be filled which can result in a relatively long time for the adhesive and/or encapsulant to set or cure during which the deep trench capacitor 134 may shift, rotate, or otherwise move. As a result, a contact surface 140 of the deep trench capacitor 134 (e.g., a surface containing contacts with which the deep trench capacitor 134 is electrically coupled to (and facing towards) the first die 106) may not be aligned (e.g., flush) with a corresponding surface 144 (also facing towards the first die 106) of the glass core 130. Such misalignment can negatively affect the ability of the deep trench capacitor 134 to electrically connect with the interconnects within the build-up regions 128 above the core 130. Furthermore, the non-homogeneity of materials within the cavity 132 (e.g., the deep trench capacitor 134 and a relatively large volume of adhesive and/or encapsulant) can create processing challenges downstream and/or increase risks of warpage, mechanical stress, and/or thermomechanical stress in the package substrate 110.
Examples disclosed herein overcome the above challenges by providing a step, platform, recessed surface, or other structure to fill much of the space within the cavity 132 and support/embed the deep trench capacitor 134 at a suitable height and at a suitable location relative to the glass core 130. For example, disclosed examples provide (e.g., pattern) such a platform in the glass core 130 via laser etching and/or wet etching. Further, disclosed examples can include platforms of varying heights, depths, etc., within the glass core 130 based on a size and/or shape of the deep trench capacitor 134 to ensure the deep trench capacitor 134 is aligned with the surface 144 of the glass core 130. For example, platforms disclosed herein can vary in shape based on a size and/or shape of the deep trench capacitor 134. Examples disclosed herein provide example platforms to support (e.g., secure) the deep trench capacitor 134 during assembly, handling, etc., of the example IC package 100. In some examples disclosed herein, adhesive material is provided in the cavity 132 to surround or otherwise contact the deep trench capacitor 134. In such examples, the platforms can provide the deep trench capacitor 134 with additional stability when the adhesive material is added (e.g., deposited, inserted, etc.) in the cavity 132. In other examples, a die attach film (DAF) may be disposed (e.g., dispensed) on the deep trench capacitor 134 to facilitate attachment to a surface of (e.g., a platform in) the cavity 132. Additionally, examples disclosed herein can provide a through glass via (TGV) that extends through the glass core 130 from the deep trench capacitor 134. Examples disclosed herein enable the IC package 100 (and the glass core 130) to include the deep trench capacitor 134 to increase (e.g., free up) signal routing in adjacent layers (e.g., the build-up regions 128) and improve the overall capacitance of the IC package 100.
As shown in
The first example surface 204 of the cavity 132 is recessed (e.g., sunken, offset, etc.) relative to the third surface 216 of the glass core 130. Additionally, the example recessed surface 206 is recessed relative to the first surface 204. Put differently, the cavity 132 may be a first example cavity, and the recessed surface 206 can define another (e.g., second) cavity within the cavity 132. Further, in some examples, the recessed surface 206 is substantially parallel (e.g., within 5 degrees) to the first surface 204.
In
The example glass core 130 includes an example via 224 that extends through the glass core 130. In particular, the example via 224 extends from the cavity 132 to a fifth example surface 226 of the glass core 130. The fifth example surface 226 opposes the third surface 216 of the glass core 130. As such, the semiconductor device 202 is positioned between the via 224 and the third surface 216. As shown in
Further, the example package substrate 200 includes the adhesive material 142 in (e.g., to fill) the via 224. The example adhesive material 142 covers an example inner wall 228 of the via 224 from the semiconductor device 202 to the fifth surface 226. Further, the example adhesive material 142 extends at least partially into the cavity 132 to contact the semiconductor device 202. For example, the adhesive material 142 can contact a sixth example surface 230 of the semiconductor device 202 (corresponding to the first side 208 of the semiconductor device 202). In this example, the adhesive material 142 may facilitate bonding between the semiconductor device 202 and the glass core 130. In some examples, the adhesive material 142 is disposed between the sixth surface 230 and the recessed surface of the recessed surface 206. In some examples, the adhesive material 142 at least partially fills the portion of the cavity 132 surrounding the semiconductor device 202 above the sixth surface 230 (e.g., bottom side) of the semiconductor device 202. For instance, in the illustrated example, the adhesive material 142 extends up to (but not onto or beyond) the first surface 204. In other examples, the adhesive material 142 is spaced apart from and below (e.g., does not extend up to) the first surface 204. In other examples, the adhesive material 142 extends beyond and onto the first surface 204. In some examples, the adhesive material 142 extends all the way up to the third surface 216 at the top of the cavity 132. In examples where the adhesive material 142 fills less than all of the open space within the cavity 132 (e.g., the space surrounding the semiconductor device 202), the remaining space within the cavity 132 may be filled with a separate dielectric material during a dielectric film lamination process performed subsequent to the stage of manufacturing represented in
Turning to
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At block 404, it is determined whether an example via is to be provided in the example glass core connected to the cavity. If no via is to be provided, the process proceeds to block 408, as discussed below in connection with
At block 406, an example via is provided in the glass core connected to the cavity. As shown in
At block 408, it is determined whether an example recessed surface is to be provided in the cavity. If no recessed surface is to be provided, the process proceeds to block 412, as discussed below in connection with
At block 410, an example recessed surface is provided in the cavity to a depth corresponding to a thickness of an example semiconductor device. As shown in
At block 412, it is determined whether example adhesive material is to be deposited (e.g., provided, applied, etc.) within the cavity or on the semiconductor device. In some examples, adhesive material may be deposited within the cavity and on the semiconductor device. If example adhesive material is to be provided on the semiconductor device, the process proceeds to block 416, as discussed below in connection with
At block 414, example adhesive material is deposited within the cavity. As shown in
At block 418, an example semiconductor device is deposited in the cavity. As shown in
Returning to block 412, if it is determined that example adhesive material is to be deposited on the semiconductor device, then the process proceeds to block 416 with the subsequent stage(s) of fabrication represented by
At block 418, the example semiconductor device is deposited in the cavity. As shown in
Returning to block 404, if it is determined that an example via is not to be provided in the glass core, then the process proceeds to block 408 with the subsequent stages of fabrication represented by
At block 410, an example recessed surface is provided in the cavity to a depth corresponding to a thickness of an example semiconductor device. As shown in
At block 412, it is determined whether example adhesive material is to be provided within the cavity or on the semiconductor device. If example adhesive material is to be provided on the semiconductor device, the process proceeds to block 416, as discussed below in connection with
At block 414, example adhesive material is deposited within the cavity. As shown in
At block 418, the example semiconductor device is deposited in the cavity. As shown in
Returning to block 412, if it is determined that example adhesive material is to be deposited on the semiconductor device, then the process proceeds to block 416 with the subsequent stage(s) of fabrication represented by
At block 418, the example semiconductor device is deposited in the cavity. As shown in
Returning to block 408, if it is determined that no recessed surface is to be provided in the cavity, then the process proceeds to block 412 with the subsequent stage(s) of fabrication represented by
At block 414, example adhesive material is deposited within the cavity. As shown in
At block 418, the example semiconductor device is added to the cavity. As shown in
Returning to block 412, if it is determined that example adhesive material is to be deposited on the semiconductor die, then the process proceeds to block 416 with the subsequent stage(s) of fabrication represented by
At block 418, the example semiconductor device is deposited in the cavity. As shown in
Returning to block 404, if it is determined that an example via is not to be provided in the glass core, then the process proceeds to block 408 with the subsequent stages of fabrication represented by
At block 412, it is determined whether example adhesive material is to be provided within the cavity or on the semiconductor device. If example adhesive material is to be provided on the semiconductor device, the process proceeds to block 416, as discussed below in connection with
At block 414, example adhesive material is deposited within the cavity. As shown in
At block 418, the example semiconductor device is added to the cavity. As shown in
Returning to block 412, if it is determined that example adhesive material is to be deposited on the semiconductor device, then the process proceeds to block 416 with the subsequent stage(s) of fabrication represented by
At block 418, the example semiconductor device is deposited in the cavity. As shown in
The example package substrates 200, 500, 600, 602, 700, 702, 800, 802 (e.g., any of the package substrates 200, 500, 600, 602, 700, 702, 800, 802 that include any of the glass cores 300, 302, 304, 306) disclosed herein may be included in any suitable electronic component, such as the example IC package 100.
The IC device 1000 may include one or more example device layers 1004 disposed on or above the die substrate 1002. The device layer 1004 may include features of one or more example transistors 1040 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. The device layer 1004 may include, for example, one or more example source and/or drain (S/D) regions 1020, an example gate 1022 to control current flow between the S/D regions 1020, and one or more example S/D contacts 1024 to route electrical signals to/from the S/D regions 1020. The transistors 1040 may include additional features not depicted for the sake of clarity such as, for example, device isolation regions, gate contacts, and the like. The transistors 1040 are not limited to the type and configuration depicted in
Some or all of the transistors 1040 may include an example gate 1022 formed of at least two layers including a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1040 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as for example a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some examples, when viewed as a cross-section of the transistor 1040 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1002 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1002. In other examples, at least one of the metal layers that form the gate electrode may be a planar layer that is substantially parallel to the top surface of the die substrate 1002 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1002. In other examples, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers include deposition and etching process steps. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1020 may be formed within the die substrate 1002 adjacent to the gate 1022 of respective ones of the transistors 1040. The S/D regions 1020 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1002 to form the S/D regions 1020. An annealing process that activates the dopants and causes the dopants to diffuse farther into the die substrate 1002 may follow the ion-implantation process. In the latter process, the die substrate 1002 may first be etched to form recesses at the locations of the S/D regions 1020. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1020. In some implementations, the S/D regions 1020 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 1020 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1020.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1040) of the device layer 1004 through one or more example interconnect layers disposed on the device layer 1004 (illustrated in
The interconnect structures 1028 may be arranged within the interconnect layers 1006-1010 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1028 depicted in
In some examples, the interconnect structures 1028 may include example lines 1028a and/or example vias 1028b filled with an electrically conductive material such as a metal. The lines 1028a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1002 upon which the device layer 1004 is formed. For example, the lines 1028a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1006-1010 may include an example dielectric material 1026 disposed between the interconnect structures 1028, as shown in
A first interconnect layer 1006 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1004. In some examples, the first interconnect layer 1006 may include lines 1028a and/or vias 1028b, as shown. The lines 1028a of the first interconnect layer 1006 may be coupled with contacts (e.g., the S/D contacts 1024) of the device layer 1004.
A second interconnect layer 1008 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1006. In some examples, the second interconnect layer 1008 may include vias 1028b to couple the lines 1028a of the second interconnect layer 1008 with the lines 1028a of the first interconnect layer 1006. Although the lines 1028a and the vias 1028b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1008) for the sake of clarity, the lines 1028a and the vias 1028b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.
A third interconnect layer 1010 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1008 according to similar techniques and configurations described in connection with the second interconnect layer 1008 and/or the first interconnect layer 1006. In some examples, the interconnect layers that are “higher up” in the metallization stack 1019 in the IC device 1000 (i.e., further away from the device layer 1004) may be thicker.
The IC device 1000 may include an example solder resist material 1034 (e.g., polyimide or similar material) and one or more example conductive contacts 1036 formed on the interconnect layers 1006-1010. In
In some examples, the circuit board 1102 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1102. In other examples, the circuit board 1102 may be a non-PCB substrate. In some examples, the circuit board 1102 may be, for example, the circuit board 102 of
The IC device assembly 1100 illustrated in
The package-on-interposer structure 1136 may include an example IC package 1120 coupled to an example interposer 1104 by example coupling components 1118. The coupling components 1118 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1116. Although a single IC package 1120 is shown in
In some examples, the interposer 1104 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 1104 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1104 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1104 may include example metal interconnects 1108 and example vias 1110, including but not limited to example through-silicon vias (TSVs) 1106. The interposer 1104 may further include example embedded devices 1114, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1104. The package-on-interposer structure 1136 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1100 may include an example IC package 1124 coupled to the first face 1140 of the circuit board 1102 by example coupling components 1122. The coupling components 1122 may take the form of any of the examples discussed above with reference to the coupling components 1116, and the IC package 1124 may take the form of any of the examples discussed above with reference to the IC package 1120.
The IC device assembly 1100 illustrated in
Additionally, in some examples, the electrical device 1200 may not include one or more of the components illustrated in
The electrical device 1200 may include example programmable or processor circuitry 1202 (e.g., one or more processing devices). The processor circuitry 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
The electrical device 1200 may include an example memory 1204, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1204 may include memory that shares a die with the processor circuitry 1202. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some examples, the electrical device 1200 may include an example communication chip 1212 (e.g., one or more communication chips). For example, the communication chip 1212 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1200. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.
The communication chip 1212 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1212 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1212 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1212 may operate in accordance with other wireless protocols in other examples. The electrical device 1200 may include an example antenna 1222 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some examples, the communication chip 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1212 may include multiple communication chips. For instance, a first communication chip 1212 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1212 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1212 may be dedicated to wireless communications, and a second communication chip 1212 may be dedicated to wired communications.
The electrical device 1200 may include example battery/power circuitry 1214. The battery/power circuitry 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1200 to an energy source separate from the electrical device 1200 (e.g., AC line power).
The electrical device 1200 may include the display 1206 (or corresponding interface circuitry, as discussed above). The display 1206 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1200 may include the audio output device 1208 (or corresponding interface circuitry, as discussed above). The audio output device 1208 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1200 may include the audio input device 1218 (or corresponding interface circuitry, as discussed above). The audio input device 1218 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1200 may include example GPS circuitry 1216. The GPS circuitry 1216 may be in communication with a satellite-based system and may receive a location of the electrical device 1200, as known in the art.
The electrical device 1200 may include any other example output device 1210 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, and/or an additional storage device.
The electrical device 1200 may include any other example input device 1220 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1220 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, and/or a radio frequency identification (RFID) reader.
The electrical device 1200 may have any desired form factor, such as, for example, a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device (e.g., a smartwatch, a ring, googles, a headset, glasses, etc.). In some examples, the electrical device 1200 may be any other electronic device that processes data.
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
Notwithstanding the foregoing, in the case of referencing a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” is not with reference to Earth, but instead is with reference to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die when the first component is farther away from a substrate (e.g., a semiconductor wafer) during fabrication/manufacturing than the second component on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied from the context, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package during fabrication when the first component is farther away from a printed circuit board (PCB) to which the IC package is to be mounted or attached. It is to be understood that semiconductor devices are often used in orientation different than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to Earth) will likely govern based on the usage context.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified herein.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
Example 1 includes a package substrate comprising a glass core having a cavity in an outer surface of the glass core, the outer surface defining a first plane, and a semiconductor die attached to a surface of the cavity, the semiconductor die having contact pads on a surface of the semiconductor die, the contact pads arranged in a second plane, the second plane substantially coplanar with the first plane.
Example 2 includes the package substrate of example 1, further including an adhesive material positioned in the cavity, the adhesive material contacting the surface of the cavity and the semiconductor die.
Example 3 includes the package substrate of example 1, wherein the surface of the cavity is a first surface, a second surface of the cavity positioned at a first angle relative to the outer surface of the glass core, and a third surface of the cavity positioned at a second angle relative to the outer surface, the second angle different than the first angle, the first surface distinct from the second surface and distinct from the third surface, the second surface distinct from the third surface.
Example 4 includes the package substrate of example 3, wherein the second angle associated with the second surface of the cavity is an acute angle.
Example 5 includes the package substrate of example 3, wherein the third surface of the cavity extends between the first surface of the cavity and the outer surface of the glass core.
Example 6 includes the package substrate of example 3, wherein the first surface of the cavity is recessed relative to the outer surface of the glass core, and the second surface of the cavity is recessed relative to the first surface of the cavity.
Example 7 includes the package substrate of example 6, further including a fourth surface of the cavity positioned between the second surface of the cavity and the outer surface of the glass core, the fourth surface of the cavity positioned at a third angle relative to the outer surface of the glass core.
Example 8 includes the package substrate of example 7, wherein the third angle associated with the fourth surface of the cavity positions the fourth surface of the cavity substantially parallel to the outer surface of the glass core.
Example 9 includes the package substrate of example 1, wherein the outer surface of the glass core is a first outer surface, the first outer surface opposing a second outer surface of the glass core, further including a via extending through the glass core from the cavity to the second outer surface.
Example 10 includes the package substrate of example 9, further including adhesive material in the via, the adhesive material extending at least partially into the cavity to contact the semiconductor die.
Example 11 includes the package substrate of example 10, wherein the adhesive material covers an inner wall of the via from the semiconductor die to the second outer surface.
Example 12 includes an integrated circuit (IC) package comprising a package substrate having a glass core including a cavity positioned in an outer surface of the glass core, and a semiconductor die supported by a recessed surface of the glass core in the cavity, the semiconductor die having a first side and a second side opposite the first side, the first side to face the recessed surface, the second side substantially flush with the outer surface of the glass core.
Example 13 includes the IC package of example 12, further including an adhesive material in the cavity to bond the semiconductor die to the glass core.
Example 14 includes the IC package of example 12, further including a via extending through the glass core, the semiconductor die positioned between the via and the outer surface of the glass core.
Example 15 includes the IC package of example 14, further including an adhesive material to fill the via, the adhesive material extending at least partially into the cavity to bond the semiconductor die to the glass core.
Example 16 includes the IC package of example 12, further including a ridge positioned in the cavity, the ridge extending from a sidewall of the cavity towards the semiconductor die and extending from the recessed surface towards the outer surface of the glass core.
Example 17 includes the IC package of example 16, wherein the ridge includes a first surface, a second surface, and a third surface, the third surface positioned between the first surface and the second surface, the first surface positioned at a first angle relative to the outer surface of the glass core, the second surface positioned at a second angle relative to the recessed surface, the third surface positioned at a third angle relative to the recessed surface.
Example 18 includes a method comprising providing a glass core, the glass core including a cavity in a surface of the glass core, and depositing a capacitor in the cavity, the cavity dimensioned to position a surface of the capacitor substantially flush with the surface of the glass core.
Example 19 includes the method of example 18, further including providing a slanted surface in the cavity, the slanted surface slanted relative to a sidewall of the cavity and slanted relative to a support surface of the cavity, the capacitor mounted to the support surface.
Example 20 includes the method of example 18, wherein the cavity includes a first cavity and a second cavity positioned in a surface of the first cavity, the capacitor mounted to a surface of the second cavity.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.
