Yi SHI

Person

Chandler, AZ, US

People

Patents Applicationslast 30 patents

Information Patent Application
SELF-ASSEMBLY METHOD AND EQUIPMENT
- Publication number 20250192096
- Publication date Jun 12, 2025
- Intel Corporation
- Yi SHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUPERHYDROPHOBIC SURFACES FOR LIQUID CONTAINMENT IN SELF-ALIGNMENT...
- Publication number 20250112185
- Publication date Apr 3, 2025
- Intel Corporation
- Thomas Sounart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES
- Publication number 20250112199
- Publication date Apr 3, 2025
- Intel Corporation
- Thomas Sounart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED AS...
- Publication number 20250112200
- Publication date Apr 3, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES
- Publication number 20250112173
- Publication date Apr 3, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT
- Publication number 20250112187
- Publication date Apr 3, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT ASSISTED ASSEMBLY ON A STRUCTURAL WAFER FOR HYBRID B...
- Publication number 20250112177
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDING STRUCTURES HAVING NON-VERTICAL EDGES FOR SELF-ALIGNMENT ASS...
- Publication number 20250112181
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR SELF-ALIGNING BATCH PICK AND PLACE DIE BO...
- Publication number 20240429199
- Publication date Dec 26, 2024
- Intel Corporation
- Yi Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR DIE-SHAPE MODIFICATION BONDING
- Publication number 20240347501
- Publication date Oct 17, 2024
- Haris Khan Niazi
- G05 - CONTROLLING REGULATING
Information Patent Application
QUASI-MONOLITHIC DIE ARCHITECTURES
- Publication number 20240063178
- Publication date Feb 22, 2024
- Intel Corporation
- Jimin Yao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEMPLATE STRUCTURE FOR QUASI-MONOLITHIC DIE ARCHITECTURES
- Publication number 20240063066
- Publication date Feb 22, 2024
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH ELECTRICALLY ACTIVE FIDUCIALS
- Publication number 20240063136
- Publication date Feb 22, 2024
- Intel Corporation
- Haris Khan Niazi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE CRACK MITIGATION IN MULTI-CHIP COMPOSITE IC STRUCTURES
- Publication number 20240063142
- Publication date Feb 22, 2024
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIDUCIAL MARKS FOR VERIFYING ALIGNMENT ACCURACY OF BONDED INTEGRATE...
- Publication number 20240006332
- Publication date Jan 4, 2024
- Intel Corporation
- Dimitrios Antartis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE TRENCH FOR IMPROVED HYBRID BONDING
- Publication number 20240006358
- Publication date Jan 4, 2024
- Intel Corporation
- Zhihua Zou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUMMY DIE PLACEMENT WITHIN A DICING STREET OF A WAFER
- Publication number 20230197520
- Publication date Jun 22, 2023
- Intel Corporation
- Yi SHI
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Applicationslast 30 patents

SELF-ASSEMBLY METHOD AND EQUIPMENT

SUPERHYDROPHOBIC SURFACES FOR LIQUID CONTAINMENT IN SELF-ALIGNMENT...

SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES

HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED AS...

PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES

IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT

SELF-ALIGNMENT ASSISTED ASSEMBLY ON A STRUCTURAL WAFER FOR HYBRID B...

BONDING STRUCTURES HAVING NON-VERTICAL EDGES FOR SELF-ALIGNMENT ASS...

METHODS AND APPARATUS FOR SELF-ALIGNING BATCH PICK AND PLACE DIE BO...

METHODS AND APPARATUS FOR DIE-SHAPE MODIFICATION BONDING

QUASI-MONOLITHIC DIE ARCHITECTURES

TEMPLATE STRUCTURE FOR QUASI-MONOLITHIC DIE ARCHITECTURES

INTEGRATED CIRCUIT DEVICE WITH ELECTRICALLY ACTIVE FIDUCIALS

DIE CRACK MITIGATION IN MULTI-CHIP COMPOSITE IC STRUCTURES

FIDUCIAL MARKS FOR VERIFYING ALIGNMENT ACCURACY OF BONDED INTEGRATE...

SUBSTRATE TRENCH FOR IMPROVED HYBRID BONDING

DUMMY DIE PLACEMENT WITHIN A DICING STREET OF A WAFER