This disclosure relates generally to semiconductor die bonding and, more particularly, to methods and apparatus for self-aligning batch pick and place die bonding.
Die-to-wafer bonding processes bond semiconductor dies directly to wafers. In die-to-wafer bonding processes, the semiconductor dies are fabricated on an initial wafer and then cut to size (e.g., singulated) prior to being placed on and bonded to the target wafer. In some instances, die-to-wafer bonding processes include fusion and/or hybrid bonding.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
Notwithstanding the foregoing, in the case of referencing a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” is not with reference to Earth, but instead is with reference to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die when the first component is farther away from a substrate (e.g., a semiconductor wafer) during fabrication/manufacturing than the second component on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied from the context, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package during fabrication when the first component is farther away from a printed circuit board (PCB) to which the IC package is to be mounted or attached. It is to be understood that semiconductor devices are often used in orientation different than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to Earth) will likely govern based on the usage context.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified in the below description.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
Traditional die-to-wafer bonding processes bond one die (e.g., semiconductor die) at a time (including flip chip bonding, thermal compression bonding (TCB), and direct hybrid bonding). In some industries, such as the micro-LED industry, die-to-wafer bonding processes can transfer multiple dies at a time, but the configuration of dies being collectively transferred is limited to multiple dies of the same type and size and arranged in a particular layout. Using such techniques, transferring and bonding different types, sizes, and/or layouts of dies would require a different process using different machinery configured for the particular dies to be transferred. Thus, transferring multiple dies based on known approaches is still a time consuming operation. As die sizes continue to get smaller, considerable time is spent placing dies one by one on a target wafer, where the target wafer may include thousands to tens of thousands of dies.
In the context of die-to-wafer bonding, hybrid bonding involves the permanent bonding of both (i) interfacing dielectric (e.g., SiOx) surfaces on the die and wafer and (ii) interfacing metal (e.g., Cu) surfaces on the die and wafer. The interfacing metal surfaces provide electrical interconnections between the die and the wafer. Hybrid bonding enables heterogeneous integration for directly connecting dies of different functions, sizes, orientations, etc.
However, no known bonding process is capable of bonding multiple dies of different types with different sizes and layouts at the same time while also allowing fine adjustments of bond placement at the die level. Collective die-to-wafer bonding allows the ability to bond multiple dies of different sizes and orientations but requires precise die placement on the wafer since the dies do not self-align. Therefore, the machinery and configurations in which dies are placed on the wafer need to be changed to accommodate different types, sizes, orientations, and/or layouts of dies for such precise die placement. This is problematic, notably, for hybrid bonding techniques where the bonding process needs to occur quickly (e.g., the fluid may evaporate) or where a wash and clean process needs to occur before the fluid is placed.
In hybrid bonding, dies are attached to the target wafer via van der Waals forces at room temperature. A thermal annealing process is applied to the entire wafer post bonding to allow covalent bonds formed between interfacing dielectric surfaces and direct copper-to-copper bonds formed between interfacing copper surfaces by diffusion.
As disclosed herein, to enable self-assembly mechanism during bonding, fluid (typically deionized (DI) water) is dispensed at bonding sites. Capillary forces in the fluid enable the dies to self-align into desired positions. In some examples, the fluid placed is very small in volume (e.g., less than 1 microliter per die) and is evaporated quickly without intervention. Therefore, the action of dispensing the fluid and placing the dies must occur quickly to prevent the fluid from evaporating before the dies are placed.
When machinery needs to change to accommodate different sized dies (and/or a different arrangement of dies), the process of placing the dies and bonding said dies to the target wafer increases production time. In some examples, the arrangement of dies to be placed on the target wafer changes with each placement of the dies, and the amount of fluid dispensed to bond those dies to the target wafer is only enough to accommodate the current arrangement of dies to be placed. With every change in machinery, there is likely a corresponding increase in production time to allow for the changing of the machinery and the halting of dispensing fluid.
Additionally, the accuracy of the machinery and configurations necessary to place the semiconductor dies to a tolerable accuracy (for example, 200 nanometers (nm) or less) is problematic. Slight variations in semiconductor die alignment on the wafer can produce non-usable components. To counter these potential misalignments, machinery may need to move slower to be more precise in picking up and placing the dies on the target wafer. Additionally, powerful vision systems are needed for the machinery to precisely align the die to target wafer during the bonding process. Also, changes to the configuration/machinery can result in the need to re-calibrate the machinery, which is costly in manufacturing time. As the tolerances decrease (for example, in tolerances less than 1 micrometer (μm)), the need for increased precision in placing the dies is imperative for creating an operable component.
By contrast, the self-aligning configuration disclosed herein does not require precise positioning of the dies due to the dies being able to self-align after placement on the target wafer in a relatively close position (e.g., within a defined tolerance). Increasing precision tolerances (e.g., allowing for greater variability) in placing dies on the target wafer subsequently result in decreases in manufacturing/production time.
Examples disclosed herein provide a configuration that can pick and place semiconductor dies of different types, sizes, orientations, and/or layouts on a wafer without the need to modify the configuration for those different arrangement of semiconductor dies. Examples disclosed herein also provide a self-aligning configuration to reduce the need for the precise placement of the semiconductor dies on the wafer.
In the example disclosed herein, the first (source) wafer 120 goes through a first preparation process 110 and the second (target) wafer 130 goes through a second preparation process 115. The first and second preparation processes 110, 115 can be performed independent of one another. Thus, in some examples, the first and second preparation processes 110, 115 are implemented in parallel. The first preparation process 110 begins with the top surface of the first wafer 120 being smoothed, flattened, or polished by a chemical mechanical planarization (CMP) process. Having a smooth and/or flat surface facilitates the hybrid bonding to occur later in the process. Once planarized, the first wafer 120 is cut (e.g., singulated, diced) to obtain semiconductor dies 135. In some examples, the semiconductor dies 135 are cut into pre-defined shapes and orientations which are determined based on the application in which the semiconductor dies 135 are to be used (e.g., a processor, memory, an integrated circuit, etc.).
The semiconductor dies 135 of the first wafer 120 are subjected to a first plasma activation 140. In some examples, the first plasma activation 140 applies a plasma treatment (e.g., using an ionized gas, such as N2, H2, and O2, to form plasma) to the semiconductor dies 135 to change the surface chemistry of bonding points (e.g., activates or energizes the surface to increase adhesion characteristics) of the semiconductor dies 135 to increase a bonding strength between the semiconductor dies 135 and the second wafer 130.
After the semiconductor dies 135 are subjected to the first plasma activation 140, the semiconductor dies 135 are subjected to a first cleaning/hydration 145. The first cleaning 145 removes any unwanted debris from the surface of the bonding points (e.g., produced from the dicing process or otherwise) and ensures that the bonding points are properly prepared for bonding. The first cleaning 145 also serves as a hydration step to increase an amount of hydroxyl (OH) groups on the surface.
The second preparation process 115 for the second (target) wafer 130 has similarities with the first preparation process 110. For instance, the second preparation process 115 begins with the top surface of the second wafer 130 undergoing a CMP process to smooth, flatten, or polish the surface. Once planarized, the second wafer 130 is subjected to a second plasma activation 150 (e.g., similar process to that of the first plasma activation 140). In some examples, the target wafer 130 is formed to include multiple materials (e.g., silicon, germanium, etc.) to create contrasting regions on the surface of the target wafer 130. In some such examples, the target wafer 130 has contrasting regions corresponding to hydrophilic regions that attract fluids and hydrophobic regions that repel fluids. The hydrophobic and hydrophilic regions are discussed further herein with respect to
In examples disclosed herein, the second plasma activation 150 activates the surface of the second wafer 130 to promote increased bonding/adhesion properties. The second plasma activation 150 ensures that the semiconductor dies 135, when placed on the second wafer 130, bond to the second wafer 130 using the die-to-wafer hybrid bonding process disclosed herein.
The second wafer 130 is subjected to a second cleaning 155. The second cleaning 155 removes any unwanted debris from the surface of the second wafer 130 and ensures that the bonding points are properly prepared for bonding, similar to that of the first cleaning 145.
To perform the die-to-wafer self-aligning and bonding process 100 disclosed herein, water droplets 160 are placed on the second wafer 130, defining where the semiconductor dies 135 are to bond to the second wafer 130. In examples disclosed herein, the water droplets 160 are placed on the hydrophilic regions of the second wafer 130. Due to the hydrophilic properties of the region, the water droplets 160 will spread out in a thin film rather than bead up on the surface. However, due to the hydrophobic regions surrounding the hydrophilic regions, the water will spread up to but not over the edge of the hydrophilic regions such that the water droplets 160 remain in the desired locations (e.g., within the hydrophilic regions) on the second wafer 130. This allows the semiconductor dies 135, once placed on the water droplets 160, to self-align through capillary forces that force the semiconductor dies 135 into alignment with the hydrophilic regions. In some examples, the amount or volume of the water droplets 160 dispensed on a given hydrophilic region is controlled to be sufficient to cover the entire hydrophobic regions with a relatively thin film layer of water having a relatively controlled volume (e.g., less than 1 microliter (μm) and can be on the nanoliter scale). Thus, larger hydrophilic regions will have more water than smaller hydrophilic regions.
After the water droplets 160 have been placed on the second wafer 130, the first and second preparation processes 110, 115 are complete and the semiconductor dies 135 are then picked up and placed on the second wafer 130 at the hydrophilic regions. While the separate preparation processes 110, 115 can be done in parallel and/or at different times, the dispensing of the water droplets 160 is done close in time to when the semiconductor dies 135 are to be transferred from the first (source) wafer 130 to the second (target) wafer 130 so that water is still present when the dies 135 are placed thereon. This timeframe is relatively small because the volume of the water droplets is relatively small and, therefore, may evaporate relatively quickly. In this example, the alignment of the semiconductor dies 135 does not need to be as precise as many known pick and place processes (e.g., sub-micron precision for existing processes while the process disclosed herein can operate properly with a precision at the tens of microns level) because the thin film layer of water that is already precisely spread across the hydrophilic region will cause a slightly misaligned die 135 to move into alignment with the underlying hydrophilic region (based on water surface tension properties and/or capillary action of the water interacting with the interfacing surface of the die 135 which is also prepared with a hydrophilic surface). Inasmuch as the self-aligning capabilities of the water enables the initial alignment of the dies from the pick and place process to be less precise than known approaches, the pick and place process disclosed herein can be done at a faster speed than known approaches.
The combined semiconductor dies 135 and second wafer 130 are then subjected to a thermal annealing process 170 to form covalent bonds at a dielectric-to-dielectric bonding interface of the dies 135 to bond the dies 135 to the second wafer 130. In some examples, the thermal annealing process 170 includes subjecting the combined semiconductor dies 135 and second wafer 130 to a temperature between 200° C.-450° C. The resulting component includes the semiconductor dies 135 fully bonded to the second wafer 130.
As discussed above, in the illustrated example of
At a first die placement stage 240 (e.g., a wafer reconstitution stage, a first pick-and-place operation) of
Transferring the dies 135, 210, 220, 230 to the carrier 260 to generate a reconstituted wafer may appear to increase production time by introducing intermediate operations of moving the dies 135, 210, 220, 230 from their original source wafers. However, this process can be performed relatively quickly because the alignment of the dies 135, 210, 220, 230 being reconstituted on the carrier 260 does not need to be very precise based on the fact that the dies 135, 210, 220, 230 will be moved again and to the final target wafer 130 and temporary misalignments will be resolved through the die-to-wafer self-aligning and bonding process 100 disclosed herein. Furthermore, by reconstituting the dies 135, 210, 220, 230 on to the carrier wafer 260, the process of moving the dies 135, 210, 220, 230 to the final target wafer 130 can be performed much more quickly because the pick-and-place assembly 250 can pick up and move multiple dies (e.g., a batch of dies) simultaneous that are already in proper arrangement relative to one another (based on the reconstitution of the dies 135, 210, 220, 230 on the carrier 260). At the first die placement stage 240, the water droplets 160 are not necessarily needed since the carrier 260 represents a temporary stage of the manufacturing process.
In some examples, once the reconstituted wafer (e.g., the carrier 260 filled with dies 135, 210, 220, 230) is created, the reconstituted wafer is taken through the first cleaning 145 as disclosed in connection with
At a second die placement stage 270, the pick-and-place assembly 250 positions the picks up the dies 135, 210, 220, 230 to place on the second wafer 130. In some examples, as represented in
Further, the pick-and-place assembly 250 is already holding a second batch 280 of the dies 135, 210, 220, 230 to be placed on the water droplets 160 that have already been dispensed onto the second wafer 130 for the second batch 280 of dies 135, 210, 220, 230. It should be understood the arrangement in which the dies 135, 210, 220, 230 are picked and placed by the pick-and-place assembly 250 is application-dependent. That is, the number, type, size, shape, and/or layout of the batch of dies picked up at a single time can differ for different applications. Thus, picking and placing such batches of dies of different dimensions reduces the time taken to transfer the dies to the second wafer 130 in combination with the reduction in precision placement of the dies because of the self-alignment of the dies. As the effect of plasma activation reduces over time, the time saved by picking and placing batches of dies can be beneficial, especially with very smaller die size (<3×3 mm) which would require huge amounts of time picking and placing one by one in some applications.
Examples disclosed herein are capable of picking and placing any suitable arrangement of dies (or any suitable number, type, size, shape, and/or layout) without a redesign or reconfiguration of the pick-and-place assembly 250. Thus, examples disclosed herein provide a universal semiconductor die pick and placement process irrespective of the arrangement of dies involved.
In some examples, the die arrangements 300, 310 correspond to a unit cell that is repeated across the wafer. The dies included in this unit cell may all be processed at a single point in time. Also shown in
The number of individual dies that can be placed on the wafer 600 is dependent on a size of the wafer 600. As illustrated in
As mentioned above, once the dies 135, 210, 220, 230 are placed on the water droplets 700, the water spreads out over the entire hydrophilic region 620, creating a boundary to align the entire dies 135, 210, 220, 230 to the wafer 600. Due to the inclusion of the hydrophobic regions 610 surrounding the hydrophilic regions 620, the water will spread up to the edge of the hydrophilic regions 620 without extending beyond this edge into the hydrophobic regions 610. This allows for less accuracy required in dispensing the water droplets 700 but still maintains precision control for which to self-align the dies 135, 210, 220, 230. This precise control with which the water spreads out enables the self-alignment of the dies 135, 210, 220, 230 by causing (through capillary forces) the dies 135, 210, 220, 230 to shift into alignment with the edge of the spread out water. By causing the dies 135, 210, 220, 230 to align with the edge of the spread out water (which is controlled by the edge of the hydrophilic regions 620), the dies 135, 210, 220, 230 will become aligned with the hydrophilic regions 620. Therefore, less accuracy is required to place the dies 135, 210, 220, 230 on the wafer 600 since the dies 135, 210, 220, 230 self-align using the water, the hydrophobic regions 610, and the hydrophilic regions 620. In some examples, the alignment accuracy achieved by this self-aligning process can be less than 200 nm.
In some examples, the water droplets 700 are dispensed on the hydrophilic regions 620 of
In the example of
As shown in
A side/cross-sectional view 1030 shows the nozzles 1020 for dispensing water/fluid onto the wafer 600, a plurality of valves 1040, a fluid source 1050, and fluid dispenser controller circuitry 1060.
The plurality of valves 1040 dispense water/fluid from the fluid source 1050 onto the wafer 600. In some examples, each valve 1040 can be controlled independently and is operably connected to the nozzles 1020. In some examples, the fluid source 1050 contains a static supply (e.g., a reservoir holding a pre-defined amount of fluid). In other examples, the fluid source 1050 contains a continuous supply of fluid (e.g., the fluid source 150 has a continuous supply of fluid). In some examples, the fluid source 1050 is a water source. In the illustrated example, the fluid source 1050 is shown as being part of the fluid dispensing assembly 1000. However, in other examples, the fluid source 1050 is separate from but fluidly coupled to the fluid dispensing assembly 1000. In some examples, the valves 1040 allow the water/fluid to flow through the valves 1040 and into the nozzles 1020 where the water/fluid is then dispensed onto the wafer 600. In some examples, the fluid dispensing assembly 1000 implements means for dispensing water on a semiconductor wafer.
The fluid dispenser controller circuitry 1060 controls the valves 1040. In some examples, the fluid dispenser controller circuitry 1060 independently controls the valves 1040 to regulate the amount of water/fluid dispensed through the nozzles 1020. In some examples, the valves 1040 are on/off valves that either block or permit fluid to be dispensed through the nozzles 1020 such that the amount of water/fluid through a given valve 1040 is controlled by how long the valve 1040 is opened. In other examples, the valves 1040 can control the flow rate of fluid through ones of the nozzles 1020 such that the amount of water/fluid is based on both how long the valve 1040 is opened and the flow rate permitted by the open valve. In some examples, where one individual nozzle 1020 may be positioned over larger hydrophilic regions 620 (e.g., corresponding to a larger die size), a larger volume of water can be dispensed through the nozzle 1020. Likewise, with smaller hydrophilic regions 620, a smaller volume of water can be dispensed through the nozzle 1020 through the independent control of the valves 1040. In other examples, a substantially consistent amount of water is dispensed through different ones of the nozzles 1020. In such examples, different amounts of water are applied to different sizes of hydrophilic regions 620 due to the number of nozzles 1020 aligned with each hydrophilic region 620. Additionally or alternatively, in some examples, at least some of the valves 1040 align with smaller hydrophilic regions 620 will remain closed to reduce the amount of water dispensed to those regions relative to larger hydrophilic regions 620. In some examples, the fluid dispenser controller circuitry 1060 implements means for regulating an amount of water/fluid to be dispensed through each nozzle 1020 of the fluid dispensing assembly 1000.
Since the fluid dispensing assembly 1000 and the pick-and-place assembly 250 of
Once the first wafer of dies is prepared, the second wafer is prepared to retain the transferred dies. (Block 1720). In some examples, preparing the second wafer includes subjecting the second wafer to a plasma activation process and a cleaning. In examples disclosed herein, the second wafer is subjected to a plasma activation process (e.g., the second plasma activation 150) to increase/improve adhesion properties on the second wafer 130 through surface chemistry modifications. Specifically, the plasma activation of the hydrophilic regions 620 ensure the bonding sites (e.g., where the dies 135, 210, 220, 230 are placed on the second wafer 130) have increased adhesion properties. In examples disclosed herein, the second wafer is subjected to a cleaning (e.g., the second cleaning 155) to ensure that no debris or foreign bodies/objects are left on the surface of the second wafer that could interfere with the bonding of the dies 135, 210, 220, 230 to the second wafer.
Once the second wafer has been prepared, the fluid dispenser controller circuitry 1060 dispenses water on the second wafer corresponding to bond sites for the dies 135, 210, 220, 230. (Block 1730). In examples disclosed herein, the water is dispensed on the second wafer by the fluid dispensing assembly 1000. In some examples, the fluid dispenser controller circuitry 1060 determines a proper amount of water to be dispensed based on the size and/or orientation of the dies 135, 210, 220, 230.
Once the water has been dispensed by the fluid dispensing assembly 1000 (as controlled by the fluid dispenser controller circuitry 1060) on the second wafer, the pick-and-place-assembly 250 picks up a set (e.g., batch) of the dies 135, 210, 220, 230. (Block 1740). In some examples, the set or batch of dies corresponds to all dies corresponding to a particular unit cell of the second wafer. In some examples, the dies 135, 210, 220, 230 picked up include dies cut from multiple different wafers (e.g., see
Once the dies 135, 210, 220, 230 have been picked up, the pick-and-place-assembly 250 places the dies 135, 210, 220, 230 on the dispensed water. (Block 1750). In examples disclosed herein, the accuracy required of the pick-and-place-assembly 250 to place the dies 135, 210, 220, 230 on the water is relatively low (e.g., a lateral offset of more than 1 μm and up to as much as 100 μm or more is acceptable) due to the capillary forces acting on the dies 135, 210, 220, 230 once placed to self-align the dies 135, 210, 220, 230 on the hydrophilic regions of the second wafer.
Once the dies 135, 210, 220, 230 have been placed, a determination is made as to whether more dies need to be placed. (Block 1760). When it is determined that more dies need to be placed (e.g., block 1760 returns a result of YES), blocks 1730 through 1760 are repeated until all dies have been placed. As discussed above, in some examples, water is dispensed (at block 1730) for a next set or batch of dies in parallel with (e.g., simultaneously with) the placement of a previous set or batch of dies.
Once all dies have been placed and a determination is made that no additional dies are to be placed (e.g., block 1760 returns a result of NO), then a thermal annealing process (e.g., the thermal annealing process 170) is performed on the second wafer with all dies having been placed on the second wafer. (Block 1770). In the examples disclosed herein, the thermal annealing process forms covalent bonds at a dielectric-to-dielectric bonding interface of the dies 135, 210, 220, 230 to bond the dies 135, 210, 220, 230 to the second wafer 130 and also facilitates the diffusion of copper between interfacing metal surfaces for direct copper-to-copper bonding.
When a determination is made that the dies 135, 210, 220, 230 will be reconstituted (e.g., block 1810 returns a result of RECONSTITUTED), a wafer (e.g., the first wafer) is cut into dies. (Block 1820). In some examples, the wafer to be cut can be cut into multiple different sizes and orientations of individual dies.
Once the wafer is cut, the cut dies are transferred to a carrier (e.g., the carrier 260 of
Once the dies are transferred to the carrier 260, a determination is made whether additional wafers are to be cut into dies. (Block 1840). When a determination is made that additional wafers are to be cut (e.g., block 1840 returns a result of YES), block 1820 through 1840 are repeated until no additional wafers are to be cut. During each iteration, the new dies (from a new wafer) are transferred to the same carrier 260, thereby reconstituting the dies from multiple wafers onto a single wafer or substrate.
When a determination is made that the dies are to be cut from a single wafer (e.g., block 1810 returns a result of SINGLE), then the first wafer is cut into dies. (Block 1850). In some examples, the dies cut from the first wafer include individual dies of different shapes and orientations to be placed on the second wafer.
Once all wafers have been cut into dies (e.g., block 1840 returns a result of NO) or when the first wafer has been cut into dies (e.g., block 1850 completes), a plasma activation process (e.g., the first plasma activation 140) is performed on the dies 135, 210, 220, 230 to modify the bonding surfaces of the dies 135, 210, 220, 230. (Block 1860). In some examples, the plasma activation process is performed to activate the dies 135, 210, 220, 230 for better adhesive properties when placed on the second wafer.
Once the plasma activation process is performed on the dies 135, 210, 220, 230, the dies 135, 210, 220, 230 are subjected to a cleaning (e.g., the first cleaning 145). (Block 1725). In some examples, the first cleaning is to ensure that no debris or foreign bodies remain on the dies 135, 210, 220, 230 before they are bonded to the second wafer.
Once the fluid dispenser controller circuitry 1060 identifies the hydrophilic regions on the second wafer, the fluid dispenser controller circuitry 1060 identifies individual areas (e.g., length by width) of the hydrophilic regions identified. (Block 1920). In some examples, the identifying of the individual areas is used to determine which nozzles 1020 are to be used to dispense the fluid/water. For example, if a nozzle 1020 is located over a region of the second wafer in which there is no hydrophilic area, then that nozzle 1020 will not be used to dispense the fluid/water.
Once the fluid dispenser controller circuitry 1060 identifies the individual areas of the hydrophilic regions, the fluid dispenser controller circuitry 1060 determines an amount of water to dispense on each hydrophilic area based on the individual areas. (Block 1930). In some examples, larger areas can take larger amounts of water to ensure that the dies 135, 210, 220, 230 will be properly aligned and bonded.
Once the fluid dispenser controller circuitry 1060 determines the amount of water to dispense on the hydrophilic areas, the fluid dispenser controller circuitry 1060 regulates the dispensing of the determined amount of water on the second wafer by controlling the valves 1040 on the fluid dispensing assembly 1000. (Block 1940). In some examples, where larger portions of water are desired, the valve 1040 for that particular nozzle 1020 is opened more than a valve 1040 that is to dispense a smaller portion of water. Additionally or alternatively, in some examples, more valves 1040 associated with nozzles 1020 aligned for the larger area are opened than for the nozzles aligned with a smaller area. In some examples, when the nozzle head is smaller than an overall area containing the hydrophilic regions to which water is to be dispensed (e.g., smaller than a full unit cell), the fluid dispenser controller circuitry 1060 can cause the nozzle head to move to different locations to facilitate the dispensing of the water. As such, each valve 1040 is controlled independently to regulate the portion of water to be dispensed based on the size, orientation, and/or arrangement of the hydrophilic regions that are to receive respective ones of the dies 135, 210, 220, 230 transferred from the first wafer.
The programmable circuitry platform 2000 of the illustrated example includes programmable circuitry 2012. The programmable circuitry 2012 of the illustrated example is hardware. For example, the programmable circuitry 2012 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The programmable circuitry 2012 may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the programmable circuitry 2012 implements the example semiconductor die to wafer self-aligning and bonding process 100 of
The programmable circuitry 2012 of the illustrated example includes a local memory 2013 (e.g., a cache, registers, etc.). The programmable circuitry 2012 of the illustrated example is in communication with main memory 2014, 2016, which includes a volatile memory 2014 and a non-volatile memory 2016, by a bus 2018. The volatile memory 2014 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory 2016 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 2014, 2016 of the illustrated example is controlled by a memory controller 2017. In some examples, the memory controller 2017 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data going to and from the main memory 2014, 2016.
The programmable circuitry platform 2000 of the illustrated example also includes interface circuitry 2020. The interface circuitry 2020 may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface.
In the illustrated example, one or more input devices 2022 are connected to the interface circuitry 2020. The input device(s) 2022 permit(s) a user (e.g., a human user, a machine user, etc.) to enter data and/or commands into the programmable circuitry 2012. The input device(s) 2022 can be implemented by, for example, a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and/or a voice recognition system.
One or more output devices 2024 are also connected to the interface circuitry 2020 of the illustrated example. The output device(s) 2024 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.). The interface circuitry 2020 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.
The interface circuitry 2020 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network 2026. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.
The programmable circuitry platform 2000 of the illustrated example also includes one or more mass storage discs or devices 2028 to store firmware, software, and/or data. Examples of such mass storage discs or devices 2028 include magnetic storage devices (e.g., floppy disk, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and/or solid-state storage discs or devices such as flash memory devices and/or SSDs.
The machine readable instructions 2032, which may be implemented by the machine readable instructions of
From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that implement methods and apparatus to self-align batch pick and place die bonding.
Example methods, apparatus, systems, and articles of manufacture to self-align batch pick and place die bonding are disclosed herein. Further examples and combinations thereof include the following:
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.