Yiu-Fai Chan

Person

Los Altos Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Delay locked loop circuitry for clock delay adjustment
- Patent number 7,308,065
- Issue date Dec 11, 2007
- Rambus Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop circuitry for clock delay adjustment
- Patent number 7,039,147
- Issue date May 2, 2006
- Rambus Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop circuitry for clock delay adjustment
- Patent number 6,539,072
- Issue date Mar 25, 2003
- Rambus, Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay-locked loop circuitry for clock delay adjustment
- Patent number 6,125,157
- Issue date Sep 26, 2000
- Rambus, Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for adjusting slew rate on an output of a drive circuit by e...
- Patent number 6,047,346
- Issue date Apr 4, 2000
- Rambus Inc.
- Benedict C. Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for the delay adjustment of a clock signal
- Patent number 5,945,862
- Issue date Aug 31, 1999
- Rambus Incorporated
- Kevin S. Donnelly
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable interface for computer system peripheral circuit card
- Patent number 5,111,423
- Issue date May 5, 1992
- Altera Corporation
- Stanley J. Kopec
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits with reduced switching noise
- Patent number 5,066,873
- Issue date Nov 19, 1991
- Altera Corporation
- Yiu-Fai Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable integrated circuit logic array device having improved...
- Patent number 4,969,121
- Issue date Nov 6, 1990
- Altera Corporation
- Yiu-Fai Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for programming and verifying programmable ele...
- Patent number 4,930,107
- Issue date May 29, 1990
- Altera Corporation
- Yiu-Fai Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array device using EPROM technology
- Patent number 4,774,421
- Issue date Sep 27, 1988
- Altera Corporation
- Robert F. Hartmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable macrocell using eprom or eeprom transistors for archit...
- Patent number 4,713,792
- Issue date Dec 15, 1987
- Altera Corporation
- Robert F. Hartmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array device using EPROM technology
- Patent number 4,617,479
- Issue date Oct 14, 1986
- Altera Corporation
- Robert F. Hartmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic array device using EPROM technology
- Patent number 4,609,986
- Issue date Sep 2, 1986
- Altera Corporation
- Robert F. Hartmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Monolithic CMOS low power digital level shifter
- Patent number 4,486,670
- Issue date Dec 4, 1984
- Intersil, Inc.
- Yiu-Fai Chan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Delay locked loop circuitry for clock delay adjustment
- Publication number 20060188051
- Publication date Aug 24, 2006
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay locked loop circuitry for clock delay adjustment
- Publication number 20040223571
- Publication date Nov 11, 2004
- Rambus Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING

Yiu-Fai Chan

Person

Patents Grantslast 30 patents

Delay locked loop circuitry for clock delay adjustment

Delay locked loop circuitry for clock delay adjustment

Delay locked loop circuitry for clock delay adjustment

Delay-locked loop circuitry for clock delay adjustment

System for adjusting slew rate on an output of a drive circuit by e...

Circuitry for the delay adjustment of a clock signal

Programmable interface for computer system peripheral circuit card

Integrated circuits with reduced switching noise

Programmable integrated circuit logic array device having improved...

Method and apparatus for programming and verifying programmable ele...

Programmable logic array device using EPROM technology

Programmable macrocell using eprom or eeprom transistors for archit...

Programmable logic array device using EPROM technology

Programmable logic array device using EPROM technology

Monolithic CMOS low power digital level shifter

Patents Applicationslast 30 patents

Delay locked loop circuitry for clock delay adjustment

Delay locked loop circuitry for clock delay adjustment